@@ -16,7 +16,9 @@ description:
properties:
compatible:
- const: atmel,sama5d2-flexcom
+ enum:
+ - atmel,sama5d2-flexcom
+ - microchip,lan966x-flexcom
reg:
maxItems: 1
@@ -46,6 +48,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
+ microchip,flx-shrd-pins:
+ description: Specify the Flexcom shared pins to be used for flexcom
+ chip-selects.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 20
+
+ microchip,flx-cs:
+ description: Flexcom chip selects. Here, value of '0' represents "cts" line
+ of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents
+ "rts" line of flexcom USART or "cs1" line of flexcom SPI.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
patternProperties:
"^serial@[0-9a-f]+$":
description: See atmel-usart.txt for details of USART bindings.
@@ -68,6 +91,18 @@ required:
- ranges
- atmel,flexcom-mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,lan966x-flexcom
+
+ then:
+ required:
+ - microchip,flx-shrd-pins
+ - microchip,flx-cs
+
additionalProperties: false
examples:
@@ -80,6 +115,8 @@ examples:
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
atmel,flexcom-mode = <2>;
+ microchip,flx-shrd-pins = <9>;
+ microchip,flx-cs = <0>;
spi0: spi@400 {
compatible = "atmel,at91rm9200-spi";
LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,flexcom.yaml | 39 ++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)