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[2a00:1450:400c:c09::233]) by mx.google.com with ESMTPS id q9si10867725wjz.241.2015.12.16.09.08.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Dec 2015 09:08:28 -0800 (PST) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 2a00:1450:400c:c09::233 as permitted sender) client-ip=2a00:1450:400c:c09::233; Authentication-Results: mx.google.com; spf=pass (google.com: domain of daniel.thompson@linaro.org designates 2a00:1450:400c:c09::233 as permitted sender) smtp.mailfrom=daniel.thompson@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-wm0-x233.google.com with SMTP id p187so10404232wmp.0 for ; Wed, 16 Dec 2015 09:08:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F3bi1+cbDqTH/f5MBleULAwOgH4VFJbN5YEoen104MI=; b=bIw0Zovsh+PupbciQD5iZfq9VmzyHqDaLdwdw07Sl0IGpw3fvrOmnorBHRM5DNUEoA 9ac5Y2tBtfxP/1I9RZemQYrx4VaxckQl3QSpDIo4VY0mXpckmdAQNYV0cu9HL9AnxkZe aTWs2N3aY6qZZyP8c5jUQ++2S1fahqoVssMbo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F3bi1+cbDqTH/f5MBleULAwOgH4VFJbN5YEoen104MI=; b=W2gdJZ9IypA+cDdStzOVwWf/mp8c39/P1v0J8O9W80NEF772n4JoS+q3HG7JHgfhQa FqrSXQpBPSFwBTrXsJo2bkDEW/EJaQscKsewHwDfFpQLo4F71RVBmRZfdOdeirHcO7P4 UArCJsF+RNMMnP8hYK8sdSlmuzKWk+QT97itc4mRfKG7NcC0tFzTCrp6N+KkSfB5fbUx HgshzYgUyTY+k9p7C5CHFYPtA4xWWfdPtUr0Xcntnnw/OEhASCqxxM/A2NNkGmIW3Z2U 5zNLNQhowJ3EB6KEgsU9ebhuo9fHRLOyI3hoWxKb/J1l0dB7bD0offrOxUWpMjQ5+q00 O3Zw== X-Gm-Message-State: ALoCoQlygu/4EkxFroKCWhkq3YqdKBps7+DpR3r0bgfI0h2D9gjv2FdRA2Lv4vf7x5dD8RtydnbHwgHQcvvuAFAl7eEgV/J6vQ== X-Received: by 10.194.178.70 with SMTP id cw6mr52070288wjc.73.1450285707366; Wed, 16 Dec 2015 09:08:27 -0800 (PST) Return-Path: Received: from wychelm.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by smtp.gmail.com with ESMTPSA id 186sm8228936wmv.9.2015.12.16.09.08.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Dec 2015 09:08:26 -0800 (PST) From: Daniel Thompson To: Russell King Cc: Daniel Thompson , Marc Zyngier , Thomas Gleixner , Jason Cooper , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: [PATCH 2/2] irqchip/gic: Identify and report any reserved SGI IDs Date: Wed, 16 Dec 2015 17:08:06 +0000 Message-Id: <1450285686-844-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1450285686-844-1-git-send-email-daniel.thompson@linaro.org> References: <1450285686-844-1-git-send-email-daniel.thompson@linaro.org> It is possible for the secure world to reserve certain SGI IDs for itself. Currently we have limited visibility of which IDs are safe to use for IPIs. Modify the GIC initialization code to actively search for reserved SGI IDs and report if any are found. Warn even more loudly if the reserved SGIs overlap with the normal IPI range. When run on an Inforce IFC6410 (Snapdragon 600) this code produces the following messages: ~~~ cut here ~~~ CPU0: Detected reserved SGI IDs: 14-15 CPU1: Detected reserved SGI IDs: 15 CPU2: Detected reserved SGI IDs: 15 CPU3: Detected reserved SGI IDs: 15 ~~~ cut here ~~~ Signed-off-by: Daniel Thompson --- drivers/irqchip/irq-gic.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) -- 2.5.0 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index abf2ffaed392..541622da7049 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -490,6 +490,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) void __iomem *base = gic_data_cpu_base(gic); unsigned int cpu_mask, cpu = smp_processor_id(); int i; + DECLARE_BITMAP(sgi_mask, 16); /* * Setting up the CPU map is only relevant for the primary GIC @@ -511,6 +512,58 @@ static void gic_cpu_init(struct gic_chip_data *gic) for (i = 0; i < NR_GIC_CPU_IF; i++) if (i != cpu) gic_cpu_map[i] &= ~cpu_mask; + + /* + * Fiddle with the SGI set/clear registers to try identify + * any IPIs that are reserved for secure world. + */ + bitmap_fill(sgi_mask, 16); + + for (i = 0; i < 16; i++) { + void __iomem *set_reg = + dist_base + GIC_DIST_SGI_PENDING_SET + (i & ~3); + void __iomem *clear_reg = + dist_base + GIC_DIST_SGI_PENDING_CLEAR + (i & ~3); + unsigned long mask = cpu_mask << (8*(i%4)); + unsigned long flags, pending, after_clear, after_set; + + local_irq_save(flags); + + /* record original value */ + pending = readl_relaxed(set_reg); + + /* clear, test, set, and test again */ + writel_relaxed(mask, clear_reg); + after_clear = readl_relaxed(set_reg); + writel_relaxed(mask, set_reg); + after_set = readl_relaxed(set_reg); + + /* restore original value */ + writel_relaxed(mask & ~pending, clear_reg); + + local_irq_restore(flags); + + if (mask & ~after_clear && mask & after_set) + clear_bit(i, sgi_mask); + } + + /* + * Show the SGI mask if it is "interesting". Here interesting + * means that the set/clear register is implemented + * (mask is not full) and it tells us that the secure world + * has reserved some SGIs (mask is not empty). + */ + if (!bitmap_full(sgi_mask, 16) && !bitmap_empty(sgi_mask, 16)) + pr_info("CPU%d: Detected reserved SGI IDs: %*pbl\n", + cpu, 16, sgi_mask); + + /* + * Yell if the reserved IDs make the system unviable. + */ + if (!bitmap_full(sgi_mask, 16) && + find_first_bit(sgi_mask, 16) < NR_IPI) + pr_crit("CPU%d: Not enough SGI IDs; expect failure\n", + cpu); } gic_cpu_config(dist_base, NULL);