arm64: Add DT support for Juno r2 board

Message ID 1450872611-15326-1-git-send-email-sudeep.holla@arm.com
State New
Headers show

Commit Message

Sudeep Holla Dec. 23, 2015, 12:10 p.m.
Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by
Cortex A72 cores.

Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

---
 Documentation/devicetree/bindings/arm/arm-boards |   1 +
 Documentation/devicetree/bindings/arm/cpus.txt   |   1 +
 arch/arm64/boot/dts/arm/Makefile                 |   2 +-
 arch/arm64/boot/dts/arm/juno-r2.dts              | 200 +++++++++++++++++++++++
 4 files changed, 203 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/arm/juno-r2.dts

-- 
1.9.1

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Comments

Rob Herring Dec. 29, 2015, 6:35 p.m. | #1
On Wed, Dec 23, 2015 at 12:10:11PM +0000, Sudeep Holla wrote:
> Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by

> Cortex A72 cores.


That's a bigger change than I'd expect...

> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

> ---

>  Documentation/devicetree/bindings/arm/arm-boards |   1 +

>  Documentation/devicetree/bindings/arm/cpus.txt   |   1 +


This should probably be a separate patch, but I already have a patch in 
my tree for 4.5 adding arm,cortex-a72. So just drop this hunk.

>  arch/arm64/boot/dts/arm/Makefile                 |   2 +-

>  arch/arm64/boot/dts/arm/juno-r2.dts              | 200 +++++++++++++++++++++++

>  4 files changed, 203 insertions(+), 1 deletion(-)

>  create mode 100644 arch/arm64/boot/dts/arm/juno-r2.dts


[...]

> +	pmu_a72 {

> +		compatible = "arm,cortex-a72-pmu";


This needs to be documented.


> +	pcie-controller@40000000 {

> +		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";


Is this common with r1?

Rob
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Sudeep Holla Dec. 30, 2015, 11:22 a.m. | #2
Hi Rob,

Thanks for the review.

On 29/12/15 18:35, Rob Herring wrote:
> On Wed, Dec 23, 2015 at 12:10:11PM +0000, Sudeep Holla wrote:

>> Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by

>> Cortex A72 cores.

>

> That's a bigger change than I'd expect...

>


I am not sure if I understood what you meant by that. Do you want me to
elaborate with more details ?

>> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

>> ---

>>   Documentation/devicetree/bindings/arm/arm-boards |   1 +

>>   Documentation/devicetree/bindings/arm/cpus.txt   |   1 +

>

> This should probably be a separate patch, but I already have a patch in

> my tree for 4.5 adding arm,cortex-a72. So just drop this hunk.

>


OK, will post DT binding separately.

>>   arch/arm64/boot/dts/arm/Makefile                 |   2 +-

>>   arch/arm64/boot/dts/arm/juno-r2.dts              | 200 +++++++++++++++++++++++

>>   4 files changed, 203 insertions(+), 1 deletion(-)

>>   create mode 100644 arch/arm64/boot/dts/arm/juno-r2.dts

>

> [...]

>

>> +	pmu_a72 {

>> +		compatible = "arm,cortex-a72-pmu";

>

> This needs to be documented.

>


Yes, Will is already carrying a patch in his tree to add this [1]

>> +	pcie-controller@40000000 {

>> +		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";

>

> Is this common with r1?

>


AFAIK it is. Liviu can you confirm ?

Regards,
Sudeep

[1] 
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/commit/?h=for-next/perf&id=5d7ee87708d4d86fcc32afc9552d05f7625d303d
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Rob Herring Dec. 30, 2015, 3:09 p.m. | #3
On Wed, Dec 30, 2015 at 5:22 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> Hi Rob,

>

> Thanks for the review.

>

> On 29/12/15 18:35, Rob Herring wrote:

>>

>> On Wed, Dec 23, 2015 at 12:10:11PM +0000, Sudeep Holla wrote:

>>>

>>> Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by

>>> Cortex A72 cores.

>>

>>

>> That's a bigger change than I'd expect...

>>

>

> I am not sure if I understood what you meant by that. Do you want me to

> elaborate with more details ?


No, just my commentary that I'd expect r1 -> r2 to be a board or Si
spin rather than a whole new core.

>>> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

>>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

>>> ---

>>>   Documentation/devicetree/bindings/arm/arm-boards |   1 +

>>>   Documentation/devicetree/bindings/arm/cpus.txt   |   1 +

>>

>>

>> This should probably be a separate patch, but I already have a patch in

>> my tree for 4.5 adding arm,cortex-a72. So just drop this hunk.

>>

>

> OK, will post DT binding separately.


No need, it is already in my tree.

>>> +       pcie-controller@40000000 {

>>> +               compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi",

>>> "pci-host-ecam-generic";

>>

>>

>> Is this common with r1?

>>

>

> AFAIK it is. Liviu can you confirm ?


Then perhaps you should move this to a common spot.

Rob
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Sudeep Holla Dec. 30, 2015, 3:34 p.m. | #4
On 30/12/15 15:09, Rob Herring wrote:
> On Wed, Dec 30, 2015 at 5:22 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:

>> Hi Rob,

>>

>> Thanks for the review.

>>

>> On 29/12/15 18:35, Rob Herring wrote:

>>>

>>> On Wed, Dec 23, 2015 at 12:10:11PM +0000, Sudeep Holla wrote:

>>>>

>>>> Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by

>>>> Cortex A72 cores.

>>>

>>>

>>> That's a bigger change than I'd expect...

>>>

>>

>> I am not sure if I understood what you meant by that. Do you want me to

>> elaborate with more details ?

>

> No, just my commentary that I'd expect r1 -> r2 to be a board or Si

> spin rather than a whole new core.

>


Ah OK, yes it's new Si and has other minor updates like latest revisions
of Cortex-A53 and other IPs. I just mentioned only the DT visible
changes in the commit log.

>>>> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

>>>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

>>>> ---

>>>>    Documentation/devicetree/bindings/arm/arm-boards |   1 +

>>>>    Documentation/devicetree/bindings/arm/cpus.txt   |   1 +

>>>

>>>

>>> This should probably be a separate patch, but I already have a patch in

>>> my tree for 4.5 adding arm,cortex-a72. So just drop this hunk.

>>>

>>

>> OK, will post DT binding separately.

>

> No need, it is already in my tree.

>


Sorry for not being clear earlier. I was referring the "arm,juno-r2"
compatible addition. I assume you have no objection if it's part of the
same patch.

>>>> +       pcie-controller@40000000 {

>>>> +               compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi",

>>>> "pci-host-ecam-generic";

>>>

>>>

>>> Is this common with r1?

>>>

>>

>> AFAIK it is. Liviu can you confirm ?

>

> Then perhaps you should move this to a common spot.

>


True, will wait for Liviu's response.

-- 
Regards,
Sudeep
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Liviu Dudau Jan. 11, 2016, 11:09 a.m. | #5
On Wed, Dec 30, 2015 at 03:34:09PM +0000, Sudeep Holla wrote:
> 

> 

> On 30/12/15 15:09, Rob Herring wrote:

> >On Wed, Dec 30, 2015 at 5:22 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:

> >>Hi Rob,

> >>

> >>Thanks for the review.

> >>

> >>On 29/12/15 18:35, Rob Herring wrote:

> >>>

> >>>On Wed, Dec 23, 2015 at 12:10:11PM +0000, Sudeep Holla wrote:

> >>>>

> >>>>Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by

> >>>>Cortex A72 cores.

> >>>

> >>>

> >>>That's a bigger change than I'd expect...

> >>>

> >>

> >>I am not sure if I understood what you meant by that. Do you want me to

> >>elaborate with more details ?

> >

> >No, just my commentary that I'd expect r1 -> r2 to be a board or Si

> >spin rather than a whole new core.

> >

> 

> Ah OK, yes it's new Si and has other minor updates like latest revisions

> of Cortex-A53 and other IPs. I just mentioned only the DT visible

> changes in the commit log.

> 

> >>>>Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>

> >>>>Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

> >>>>---

> >>>>   Documentation/devicetree/bindings/arm/arm-boards |   1 +

> >>>>   Documentation/devicetree/bindings/arm/cpus.txt   |   1 +

> >>>

> >>>

> >>>This should probably be a separate patch, but I already have a patch in

> >>>my tree for 4.5 adding arm,cortex-a72. So just drop this hunk.

> >>>

> >>

> >>OK, will post DT binding separately.

> >

> >No need, it is already in my tree.

> >

> 

> Sorry for not being clear earlier. I was referring the "arm,juno-r2"

> compatible addition. I assume you have no objection if it's part of the

> same patch.

> 

> >>>>+       pcie-controller@40000000 {

> >>>>+               compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi",

> >>>>"pci-host-ecam-generic";

> >>>

> >>>

> >>>Is this common with r1?

> >>>

> >>

> >>AFAIK it is. Liviu can you confirm ?

> >

> >Then perhaps you should move this to a common spot.

> >

> 

> True, will wait for Liviu's response.


AFAIK Juno r2 should have identical PCIe controller to r1. I have not been able to
test it myself but at the same time I have no information on any changes applied to
the IP.

Sudeep, probably worth moving the pcie-controller@40000000 node in juno-base.dtsi
and disable it by default, then re-enable in juno-r1.dts and juno-r2.dts.

Best regards,
Liviu

> 

> -- 

> Regards,

> Sudeep

> 


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Sudeep Holla Jan. 11, 2016, 11:12 a.m. | #6
On 11/01/16 11:09, Liviu Dudau wrote:
> On Wed, Dec 30, 2015 at 03:34:09PM +0000, Sudeep Holla wrote:


[...]

>>>>

>>>> AFAIK it is. Liviu can you confirm ?

>>>

>>> Then perhaps you should move this to a common spot.

>>>

>>

>> True, will wait for Liviu's response.

>

> AFAIK Juno r2 should have identical PCIe controller to r1. I have not been able to

> test it myself but at the same time I have no information on any changes applied to

> the IP.

>

> Sudeep, probably worth moving the pcie-controller@40000000 node in juno-base.dtsi

> and disable it by default, then re-enable in juno-r1.dts and juno-r2.dts.

>


Yes, that's exactly what I though as it's present even on R0 but
disabled due to H/W bug. I will do that and repost after merge window.

-- 
Regards,
Sudeep
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Patch

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 1a709970e7f7..70601a58c433 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -180,6 +180,7 @@  described under the RS1 memory mapping.
 Required properties (in root node):
 	compatible = "arm,juno";	/* For Juno r0 board */
 	compatible = "arm,juno-r1";	/* For Juno r1 board */
+	compatible = "arm,juno-r2";	/* For Juno r2 board */
 
 Required nodes:
 The description for the board must include:
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87fef20..58e240d75169 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -157,6 +157,7 @@  nodes to be present and contain the properties described below.
 			    "arm,cortex-a17"
 			    "arm,cortex-a53"
 			    "arm,cortex-a57"
+			    "arm,cortex-a72"
 			    "arm,cortex-m0"
 			    "arm,cortex-m0+"
 			    "arm,cortex-m1"
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index bb3c07209676..c0bf56b9ce3d 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -1,5 +1,5 @@ 
 dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
-dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
new file mode 100644
index 000000000000..7ca939032373
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -0,0 +1,200 @@ 
+/*
+ * ARM Ltd. Juno Platform
+ *
+ * Copyright (c) 2015 ARM Ltd.
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "ARM Juno development board (r2)";
+	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &soc_uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&A72_0>;
+				};
+				core1 {
+					cpu = <&A72_1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&A53_0>;
+				};
+				core1 {
+					cpu = <&A53_1>;
+				};
+				core2 {
+					cpu = <&A53_2>;
+				};
+				core3 {
+					cpu = <&A53_3>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "arm,psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <300>;
+				exit-latency-us = <1200>;
+				min-residency-us = <2000>;
+			};
+
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x1010000>;
+				local-timer-stop;
+				entry-latency-us = <300>;
+				exit-latency-us = <1200>;
+				min-residency-us = <2500>;
+			};
+		};
+
+		A72_0: cpu@0 {
+			compatible = "arm,cortex-a72","arm,armv8";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A72_L2>;
+			clocks = <&scpi_dvfs 0>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A72_1: cpu@1 {
+			compatible = "arm,cortex-a72","arm,armv8";
+			reg = <0x0 0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A72_L2>;
+			clocks = <&scpi_dvfs 0>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A53_0: cpu@100 {
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			clocks = <&scpi_dvfs 1>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A53_1: cpu@101 {
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x101>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			clocks = <&scpi_dvfs 1>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A53_2: cpu@102 {
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x102>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			clocks = <&scpi_dvfs 1>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A53_3: cpu@103 {
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x103>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			clocks = <&scpi_dvfs 1>;
+			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+		};
+
+		A72_L2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		A53_L2: l2-cache1 {
+			compatible = "cache";
+		};
+	};
+
+	pmu_a72 {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A72_0>,
+				     <&A72_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A53_0>,
+				     <&A53_1>,
+				     <&A53_2>,
+				     <&A53_3>;
+	};
+
+	#include "juno-base.dtsi"
+
+	pcie-controller@40000000 {
+		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
+		device_type = "pci";
+		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
+		bus-range = <0 255>;
+		linux,pci-domain = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		dma-coherent;
+		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
+			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
+			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
+				<0 0 0 2 &gic 0 0 0 137 4>,
+				<0 0 0 3 &gic 0 0 0 138 4>,
+				<0 0 0 4 &gic 0 0 0 139 4>;
+		msi-parent = <&v2m_0>;
+	};
+};
+
+&memtimer {
+	status = "okay";
+};