| Message ID | 1658316144-16520-3-git-send-email-quic_c_skakit@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
Quoting Satya Priya (2022-07-20 04:22:24) > From: Taniya Das <quic_tdas@quicinc.com> > > The lpass audio supports TX/RX/WSA block resets. Also to keep > consistency update lpasscore to lpass_core. Consistency with what? > > Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> > --- > Changes since v3: > - Remove the status="disabled" from lpasscc node. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 71735bb..c641f0b 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2184,6 +2184,7 @@ > power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > #clock-cells = <1>; > #power-domain-cells = <1>; > + #reset-cells = <1>; Is there a binding update for qcom,sc7280-lpassaudiocc? > }; > > lpass_aon: clock-controller@3380000 { > @@ -2191,13 +2192,13 @@ > reg = <0 0x03380000 0 0x30000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&rpmhcc RPMH_CXO_CLK_A>, > - <&lpasscore LPASS_CORE_CC_CORE_CLK>; > + <&lpass_core LPASS_CORE_CC_CORE_CLK>; Is this really necessary? > clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; > #clock-cells = <1>; > #power-domain-cells = <1>; > }; > > - lpasscore: clock-controller@3900000 { > + lpass_core: clock-controller@3900000 { Is this really necessary? > compatible = "qcom,sc7280-lpasscorecc"; > reg = <0 0x03900000 0 0x50000>; > clocks = <&rpmhcc RPMH_CXO_CLK>;
On 7/27/2022 6:52 AM, Stephen Boyd wrote: > Quoting Satya Priya (2022-07-20 04:22:24) >> From: Taniya Das <quic_tdas@quicinc.com> >> >> The lpass audio supports TX/RX/WSA block resets. Also to keep >> consistency update lpasscore to lpass_core. > Consistency with what? Hi Stephen, We got a comment to change this on previous posts, to keep consistency with the other nodes like lpass_aon etc https://patchwork.kernel.org/project/linux-arm-msm/patch/20220503113246.13857-1-quic_tdas@quicinc.com/#24842497 >> Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> >> --- >> Changes since v3: >> - Remove the status="disabled" from lpasscc node. >> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 71735bb..c641f0b 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2184,6 +2184,7 @@ >> power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; >> #clock-cells = <1>; >> #power-domain-cells = <1>; >> + #reset-cells = <1>; > Is there a binding update for qcom,sc7280-lpassaudiocc? > >> }; >> >> lpass_aon: clock-controller@3380000 { >> @@ -2191,13 +2192,13 @@ >> reg = <0 0x03380000 0 0x30000>; >> clocks = <&rpmhcc RPMH_CXO_CLK>, >> <&rpmhcc RPMH_CXO_CLK_A>, >> - <&lpasscore LPASS_CORE_CC_CORE_CLK>; >> + <&lpass_core LPASS_CORE_CC_CORE_CLK>; > Is this really necessary? > >> clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; >> #clock-cells = <1>; >> #power-domain-cells = <1>; >> }; >> >> - lpasscore: clock-controller@3900000 { >> + lpass_core: clock-controller@3900000 { > Is this really necessary? > >> compatible = "qcom,sc7280-lpasscorecc"; >> reg = <0 0x03900000 0 0x50000>; >> clocks = <&rpmhcc RPMH_CXO_CLK>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 71735bb..c641f0b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2184,6 +2184,7 @@ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; lpass_aon: clock-controller@3380000 { @@ -2191,13 +2192,13 @@ reg = <0 0x03380000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&lpasscore LPASS_CORE_CC_CORE_CLK>; + <&lpass_core LPASS_CORE_CC_CORE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; #clock-cells = <1>; #power-domain-cells = <1>; }; - lpasscore: clock-controller@3900000 { + lpass_core: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; clocks = <&rpmhcc RPMH_CXO_CLK>;