[4/6] EEYNOS: Add SMDK5250 board support

Message ID 1324551168-1202-5-git-send-email-chander.kashyap@linaro.org
State Superseded
Headers show

Commit Message

Chander Kashyap Dec. 22, 2011, 10:52 a.m.
SMDK5250 board is based on Samsungs EXYNOS5250 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
 MAINTAINERS                                      |    1 +
 arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
 arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
 arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
 arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
 arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
 arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
 arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
 arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
 board/samsung/smdk5250/Makefile                  |   48 ++
 board/samsung/smdk5250/lowlevel_init.S           |  524 +++++++++++++++++++
 board/samsung/smdk5250/mem_setup.S               |  600 ++++++++++++++++++++++
 board/samsung/smdk5250/smdk5250.c                |  125 +++++
 board/samsung/smdk5250/smdk5250_setup.h          |  583 +++++++++++++++++++++
 boards.cfg                                       |    1 +
 include/configs/smdk5250.h                       |  182 +++++++
 16 files changed, 2867 insertions(+), 272 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
 create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
 create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
 create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
 create mode 100644 board/samsung/smdk5250/Makefile
 create mode 100644 board/samsung/smdk5250/lowlevel_init.S
 create mode 100644 board/samsung/smdk5250/mem_setup.S
 create mode 100644 board/samsung/smdk5250/smdk5250.c
 create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
 create mode 100644 include/configs/smdk5250.h

Comments

Minkyu Kang Dec. 23, 2011, 4:21 a.m. | #1
Dear Chander Kashyap,

On 22 December 2011 19:52, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
>
> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> ---
>  MAINTAINERS                                      |    1 +
>  arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
>  arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
>  arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
>  arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
>  arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
>  arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
>  arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
>  arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
>  board/samsung/smdk5250/Makefile                  |   48 ++
>  board/samsung/smdk5250/lowlevel_init.S           |  524 +++++++++++++++++++
>  board/samsung/smdk5250/mem_setup.S               |  600 ++++++++++++++++++++++
>  board/samsung/smdk5250/smdk5250.c                |  125 +++++
>  board/samsung/smdk5250/smdk5250_setup.h          |  583 +++++++++++++++++++++
>  boards.cfg                                       |    1 +
>  include/configs/smdk5250.h                       |  182 +++++++
>  16 files changed, 2867 insertions(+), 272 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
>  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
>  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
>  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
>  create mode 100644 board/samsung/smdk5250/Makefile
>  create mode 100644 board/samsung/smdk5250/lowlevel_init.S
>  create mode 100644 board/samsung/smdk5250/mem_setup.S
>  create mode 100644 board/samsung/smdk5250/smdk5250.c
>  create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
>  create mode 100644 include/configs/smdk5250.h

Please split this patch for board and SoC.

>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a56ca10..abf88be 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -704,6 +704,7 @@ Chander Kashyap <k.chander@samsung.com>
>
>        origen                  ARM ARMV7 (EXYNOS4210 SoC)
>        SMDKV310                ARM ARMV7 (EXYNOS4210 SoC)
> +       SMDK5250                ARM ARMV7 (EXYNOS5250 SoC)
>
>  Torsten Koschorrek <koschorrek@synertronixx.de>
>        scb9328         ARM920T (i.MXL)
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index b101f96..88e2fc0 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>
>        if (s5p_get_cpu_rev() == 0) {
>                /*
> -                * CLK_SRC_PERIL0
> +                * CLK_SRC_{PERIL0 | PERIC0}
>                 * PWM_SEL [27:24]
>                 */
> +#ifdef CONFIG_EXYNOS5
> +               sel = readl(&clk->src_peric0);
> +#else
>                sel = readl(&clk->src_peril0);
> +#endif

NAK.
We don't allow to using ifdef for separating SoCs.
Please refer s5pc1xx case for solve it.
This comment apply to this patch globally.
Please remove '#ifdef CONFIG_EXYNOS5'.

Thanks.
Minkyu Kang.
Chander Kashyap Dec. 23, 2011, 5:51 a.m. | #2
Dear Minkyu Kang,

On 23 December 2011 09:51, Minkyu Kang <promsoft@gmail.com> wrote:
>
> Dear Chander Kashyap,
>
> On 22 December 2011 19:52, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> > SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
> >
> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> > ---
> >  MAINTAINERS                                      |    1 +
> >  arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
> >  arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
> >  arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
> >  arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
> >  arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
> >  arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
> >  arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
> >  arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
> >  board/samsung/smdk5250/Makefile                  |   48 ++
> >  board/samsung/smdk5250/lowlevel_init.S           |  524 +++++++++++++++++++
> >  board/samsung/smdk5250/mem_setup.S               |  600 ++++++++++++++++++++++
> >  board/samsung/smdk5250/smdk5250.c                |  125 +++++
> >  board/samsung/smdk5250/smdk5250_setup.h          |  583 +++++++++++++++++++++
> >  boards.cfg                                       |    1 +
> >  include/configs/smdk5250.h                       |  182 +++++++
> >  16 files changed, 2867 insertions(+), 272 deletions(-)
> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
> >  create mode 100644 board/samsung/smdk5250/Makefile
> >  create mode 100644 board/samsung/smdk5250/lowlevel_init.S
> >  create mode 100644 board/samsung/smdk5250/mem_setup.S
> >  create mode 100644 board/samsung/smdk5250/smdk5250.c
> >  create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
> >  create mode 100644 include/configs/smdk5250.h
>
> Please split this patch for board and SoC.

Ok
>
>
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index a56ca10..abf88be 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -704,6 +704,7 @@ Chander Kashyap <k.chander@samsung.com>
> >
> >        origen                  ARM ARMV7 (EXYNOS4210 SoC)
> >        SMDKV310                ARM ARMV7 (EXYNOS4210 SoC)
> > +       SMDK5250                ARM ARMV7 (EXYNOS5250 SoC)
> >
> >  Torsten Koschorrek <koschorrek@synertronixx.de>
> >        scb9328         ARM920T (i.MXL)
> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> > index b101f96..88e2fc0 100644
> > --- a/arch/arm/cpu/armv7/exynos/clock.c
> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
> >
> >        if (s5p_get_cpu_rev() == 0) {
> >                /*
> > -                * CLK_SRC_PERIL0
> > +                * CLK_SRC_{PERIL0 | PERIC0}
> >                 * PWM_SEL [27:24]
> >                 */
> > +#ifdef CONFIG_EXYNOS5
> > +               sel = readl(&clk->src_peric0);
> > +#else
> >                sel = readl(&clk->src_peril0);
> > +#endif
>
> NAK.
> We don't allow to using ifdef for separating SoCs.
> Please refer s5pc1xx case for solve it.
> This comment apply to this patch globally.
> Please remove '#ifdef CONFIG_EXYNOS5'.
>
I have tried to reuse the code. It is possible to remove
#ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
Is it a acceptable solution? Or is it necessary to write SoC specific function
in clock.c as done in case of s5pc1xx/clock.c.

Please Advice
>
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net




--
with warm regards,
Chander Kashyap
Sachin Kamat Dec. 23, 2011, 5:58 a.m. | #3
Hi Chander,

Subject line of patch: s/EEYNOS/EXYNOS

On 23 December 2011 11:21, Chander Kashyap <chander.kashyap@linaro.org>wrote:

> Dear Minkyu Kang,
>
> On 23 December 2011 09:51, Minkyu Kang <promsoft@gmail.com> wrote:
> >
> > Dear Chander Kashyap,
> >
> > On 22 December 2011 19:52, Chander Kashyap <chander.kashyap@linaro.org>
> wrote:
> > > SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
> > >
> > > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> > > ---
> > >  MAINTAINERS                                      |    1 +
> > >  arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
> > >  arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
> > >  arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
> > >  arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
> > >  arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
> > >  arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
> > >  arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
> > >  arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
> > >  board/samsung/smdk5250/Makefile                  |   48 ++
> > >  board/samsung/smdk5250/lowlevel_init.S           |  524
> +++++++++++++++++++
> > >  board/samsung/smdk5250/mem_setup.S               |  600
> ++++++++++++++++++++++
> > >  board/samsung/smdk5250/smdk5250.c                |  125 +++++
> > >  board/samsung/smdk5250/smdk5250_setup.h          |  583
> +++++++++++++++++++++
> > >  boards.cfg                                       |    1 +
> > >  include/configs/smdk5250.h                       |  182 +++++++
> > >  16 files changed, 2867 insertions(+), 272 deletions(-)
> > >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
> > >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
> > >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
> > >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
> > >  create mode 100644 board/samsung/smdk5250/Makefile
> > >  create mode 100644 board/samsung/smdk5250/lowlevel_init.S
> > >  create mode 100644 board/samsung/smdk5250/mem_setup.S
> > >  create mode 100644 board/samsung/smdk5250/smdk5250.c
> > >  create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
> > >  create mode 100644 include/configs/smdk5250.h
> >
> > Please split this patch for board and SoC.
>
> Ok
> >
> >
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index a56ca10..abf88be 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -704,6 +704,7 @@ Chander Kashyap <k.chander@samsung.com>
> > >
> > >        origen                  ARM ARMV7 (EXYNOS4210 SoC)
> > >        SMDKV310                ARM ARMV7 (EXYNOS4210 SoC)
> > > +       SMDK5250                ARM ARMV7 (EXYNOS5250 SoC)
> > >
> > >  Torsten Koschorrek <koschorrek@synertronixx.de>
> > >        scb9328         ARM920T (i.MXL)
> > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> > > index b101f96..88e2fc0 100644
> > > --- a/arch/arm/cpu/armv7/exynos/clock.c
> > > +++ b/arch/arm/cpu/armv7/exynos/clock.c
> > > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
> > >
> > >        if (s5p_get_cpu_rev() == 0) {
> > >                /*
> > > -                * CLK_SRC_PERIL0
> > > +                * CLK_SRC_{PERIL0 | PERIC0}
> > >                 * PWM_SEL [27:24]
> > >                 */
> > > +#ifdef CONFIG_EXYNOS5
> > > +               sel = readl(&clk->src_peric0);
> > > +#else
> > >                sel = readl(&clk->src_peril0);
> > > +#endif
> >
> > NAK.
> > We don't allow to using ifdef for separating SoCs.
> > Please refer s5pc1xx case for solve it.
> > This comment apply to this patch globally.
> > Please remove '#ifdef CONFIG_EXYNOS5'.
> >
> I have tried to reuse the code. It is possible to remove
> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
> Is it a acceptable solution? Or is it necessary to write SoC specific
> function
> in clock.c as done in case of s5pc1xx/clock.c.
>
> Please Advice
> >
> > Thanks.
> > Minkyu Kang.
> > --
> > from. prom.
> > www.promsoft.net
>
>
>
>
> --
> with warm regards,
> Chander Kashyap
>
> _______________________________________________
> Samsung mailing list
> Samsung@lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/samsung
>
Chander Kashyap Dec. 27, 2011, 8:48 a.m. | #4
Dear minkyu Kang

On 23 December 2011 11:21, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> Dear Minkyu Kang,
>
> On 23 December 2011 09:51, Minkyu Kang <promsoft@gmail.com> wrote:
>>
>> Dear Chander Kashyap,
>>
>> On 22 December 2011 19:52, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>> > SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
>> >
>> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
>> > ---
>> >  MAINTAINERS                                      |    1 +
>> >  arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
>> >  arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
>> >  arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
>> >  arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
>> >  arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
>> >  arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
>> >  arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
>> >  arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
>> >  board/samsung/smdk5250/Makefile                  |   48 ++
>> >  board/samsung/smdk5250/lowlevel_init.S           |  524 +++++++++++++++++++
>> >  board/samsung/smdk5250/mem_setup.S               |  600 ++++++++++++++++++++++
>> >  board/samsung/smdk5250/smdk5250.c                |  125 +++++
>> >  board/samsung/smdk5250/smdk5250_setup.h          |  583 +++++++++++++++++++++
>> >  boards.cfg                                       |    1 +
>> >  include/configs/smdk5250.h                       |  182 +++++++
>> >  16 files changed, 2867 insertions(+), 272 deletions(-)
>> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
>> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
>> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
>> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
>> >  create mode 100644 board/samsung/smdk5250/Makefile
>> >  create mode 100644 board/samsung/smdk5250/lowlevel_init.S
>> >  create mode 100644 board/samsung/smdk5250/mem_setup.S
>> >  create mode 100644 board/samsung/smdk5250/smdk5250.c
>> >  create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
>> >  create mode 100644 include/configs/smdk5250.h
>>
>> Please split this patch for board and SoC.
>
> Ok
>>
>>
>> >
>> > diff --git a/MAINTAINERS b/MAINTAINERS
>> > index a56ca10..abf88be 100644
>> > --- a/MAINTAINERS
>> > +++ b/MAINTAINERS
>> > @@ -704,6 +704,7 @@ Chander Kashyap <k.chander@samsung.com>
>> >
>> >        origen                  ARM ARMV7 (EXYNOS4210 SoC)
>> >        SMDKV310                ARM ARMV7 (EXYNOS4210 SoC)
>> > +       SMDK5250                ARM ARMV7 (EXYNOS5250 SoC)
>> >
>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>> >        scb9328         ARM920T (i.MXL)
>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>> > index b101f96..88e2fc0 100644
>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>> >
>> >        if (s5p_get_cpu_rev() == 0) {
>> >                /*
>> > -                * CLK_SRC_PERIL0
>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>> >                 * PWM_SEL [27:24]
>> >                 */
>> > +#ifdef CONFIG_EXYNOS5
>> > +               sel = readl(&clk->src_peric0);
>> > +#else
>> >                sel = readl(&clk->src_peril0);
>> > +#endif
>>
>> NAK.
>> We don't allow to using ifdef for separating SoCs.
>> Please refer s5pc1xx case for solve it.
>> This comment apply to this patch globally.
>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>
> I have tried to reuse the code. It is possible to remove
> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
> Is it a acceptable solution? Or is it necessary to write SoC specific function
> in clock.c as done in case of s5pc1xx/clock.c.
>
> Please Advice
Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
reuse the code in clock.c.
What is the technical hindrance of not using ifdefs?

What are yours comments regarding this issue?
>>
>> Thanks.
>> Minkyu Kang.
>> --
>> from. prom.
>> www.promsoft.net
>
>
>
>
> --
> with warm regards,
> Chander Kashyap
Chander Kashyap Jan. 5, 2012, 6:08 a.m. | #5
Dear Minkyu Kang,

On 27 December 2011 14:18, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> Dear minkyu Kang
>
> On 23 December 2011 11:21, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>> Dear Minkyu Kang,
>>
>> On 23 December 2011 09:51, Minkyu Kang <promsoft@gmail.com> wrote:
>>>
>>> Dear Chander Kashyap,
>>>
>>> On 22 December 2011 19:52, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>>> > SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
>>> >
>>> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
>>> > ---
>>> >  MAINTAINERS                                      |    1 +
>>> >  arch/arm/cpu/armv7/exynos/clock.c                |   24 +-
>>> >  arch/arm/include/asm/arch-exynos/clock.h         |  232 +--------
>>> >  arch/arm/include/asm/arch-exynos/clock_exynos4.h |  255 +++++++++
>>> >  arch/arm/include/asm/arch-exynos/clock_exynos5.h |  352 +++++++++++++
>>> >  arch/arm/include/asm/arch-exynos/cpu.h           |   71 ++--
>>> >  arch/arm/include/asm/arch-exynos/cpu_exynos4.h   |   51 ++
>>> >  arch/arm/include/asm/arch-exynos/cpu_exynos5.h   |   39 ++
>>> >  arch/arm/include/asm/arch-exynos/gpio.h          |   51 ++-
>>> >  board/samsung/smdk5250/Makefile                  |   48 ++
>>> >  board/samsung/smdk5250/lowlevel_init.S           |  524 +++++++++++++++++++
>>> >  board/samsung/smdk5250/mem_setup.S               |  600 ++++++++++++++++++++++
>>> >  board/samsung/smdk5250/smdk5250.c                |  125 +++++
>>> >  board/samsung/smdk5250/smdk5250_setup.h          |  583 +++++++++++++++++++++
>>> >  boards.cfg                                       |    1 +
>>> >  include/configs/smdk5250.h                       |  182 +++++++
>>> >  16 files changed, 2867 insertions(+), 272 deletions(-)
>>> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos4.h
>>> >  create mode 100644 arch/arm/include/asm/arch-exynos/clock_exynos5.h
>>> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos4.h
>>> >  create mode 100644 arch/arm/include/asm/arch-exynos/cpu_exynos5.h
>>> >  create mode 100644 board/samsung/smdk5250/Makefile
>>> >  create mode 100644 board/samsung/smdk5250/lowlevel_init.S
>>> >  create mode 100644 board/samsung/smdk5250/mem_setup.S
>>> >  create mode 100644 board/samsung/smdk5250/smdk5250.c
>>> >  create mode 100644 board/samsung/smdk5250/smdk5250_setup.h
>>> >  create mode 100644 include/configs/smdk5250.h
>>>
>>> Please split this patch for board and SoC.
>>
>> Ok
>>>
>>>
>>> >
>>> > diff --git a/MAINTAINERS b/MAINTAINERS
>>> > index a56ca10..abf88be 100644
>>> > --- a/MAINTAINERS
>>> > +++ b/MAINTAINERS
>>> > @@ -704,6 +704,7 @@ Chander Kashyap <k.chander@samsung.com>
>>> >
>>> >        origen                  ARM ARMV7 (EXYNOS4210 SoC)
>>> >        SMDKV310                ARM ARMV7 (EXYNOS4210 SoC)
>>> > +       SMDK5250                ARM ARMV7 (EXYNOS5250 SoC)
>>> >
>>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>>> >        scb9328         ARM920T (i.MXL)
>>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>> > index b101f96..88e2fc0 100644
>>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>>> >
>>> >        if (s5p_get_cpu_rev() == 0) {
>>> >                /*
>>> > -                * CLK_SRC_PERIL0
>>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>>> >                 * PWM_SEL [27:24]
>>> >                 */
>>> > +#ifdef CONFIG_EXYNOS5
>>> > +               sel = readl(&clk->src_peric0);
>>> > +#else
>>> >                sel = readl(&clk->src_peril0);
>>> > +#endif
>>>
>>> NAK.
>>> We don't allow to using ifdef for separating SoCs.
>>> Please refer s5pc1xx case for solve it.
>>> This comment apply to this patch globally.
>>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>>
>> I have tried to reuse the code. It is possible to remove
>> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
>> Is it a acceptable solution? Or is it necessary to write SoC specific function
>> in clock.c as done in case of s5pc1xx/clock.c.
>>
>> Please Advice
> Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
> reuse the code in clock.c.
> What is the technical hindrance of not using ifdefs?
>
> What are yours comments regarding this issue?
Any comments regrading the above discussion ?
>>>
>>> Thanks.
>>> Minkyu Kang.
>>> --
>>> from. prom.
>>> www.promsoft.net
>>
>>
>>
>>
>> --
>> with warm regards,
>> Chander Kashyap
>
>
>
> --
> with warm regards,
> Chander Kashyap
Minkyu Kang Jan. 5, 2012, 6:43 a.m. | #6
Dear Chander Kashyap,

On 27 December 2011 17:48, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>>> >        scb9328         ARM920T (i.MXL)
>>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>> > index b101f96..88e2fc0 100644
>>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>>> >
>>> >        if (s5p_get_cpu_rev() == 0) {
>>> >                /*
>>> > -                * CLK_SRC_PERIL0
>>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>>> >                 * PWM_SEL [27:24]
>>> >                 */
>>> > +#ifdef CONFIG_EXYNOS5
>>> > +               sel = readl(&clk->src_peric0);
>>> > +#else
>>> >                sel = readl(&clk->src_peril0);
>>> > +#endif
>>>
>>> NAK.
>>> We don't allow to using ifdef for separating SoCs.
>>> Please refer s5pc1xx case for solve it.
>>> This comment apply to this patch globally.
>>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>>
>> I have tried to reuse the code. It is possible to remove
>> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
>> Is it a acceptable solution? Or is it necessary to write SoC specific function
>> in clock.c as done in case of s5pc1xx/clock.c.
>>
>> Please Advice
> Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
> reuse the code in clock.c.
> What is the technical hindrance of not using ifdefs?

No need to reuse the code, if SoCs are different.
If need, please separate the functions.

like this,

unsigned long get_arm_clk(void)
{
	if (cpu_is_s5pc110())
		return s5pc110_get_arm_clk();
	else
		return s5pc100_get_arm_clk();
}

Thanks.
Minkyu Kang
Chander Kashyap Jan. 5, 2012, 10:31 a.m. | #7
Hi Minkyu Kang,

On 5 January 2012 12:13, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Chander Kashyap,
>
> On 27 December 2011 17:48, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>>>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>>>> >        scb9328         ARM920T (i.MXL)
>>>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>>> > index b101f96..88e2fc0 100644
>>>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>>>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>>>> >
>>>> >        if (s5p_get_cpu_rev() == 0) {
>>>> >                /*
>>>> > -                * CLK_SRC_PERIL0
>>>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>>>> >                 * PWM_SEL [27:24]
>>>> >                 */
>>>> > +#ifdef CONFIG_EXYNOS5
>>>> > +               sel = readl(&clk->src_peric0);
>>>> > +#else
>>>> >                sel = readl(&clk->src_peril0);
>>>> > +#endif
>>>>
>>>> NAK.
>>>> We don't allow to using ifdef for separating SoCs.
>>>> Please refer s5pc1xx case for solve it.
>>>> This comment apply to this patch globally.
>>>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>>>
>>> I have tried to reuse the code. It is possible to remove
>>> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
>>> Is it a acceptable solution? Or is it necessary to write SoC specific function
>>> in clock.c as done in case of s5pc1xx/clock.c.
>>>
>>> Please Advice
>> Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
>> reuse the code in clock.c.
>> What is the technical hindrance of not using ifdefs?
>
> No need to reuse the code, if SoCs are different.
> If need, please separate the functions.

Yes, though SoC's are different, the functionality in clock.c is
similar. The only difference is the clock name in the clock structure
for Exynos4 and Exynos5 but the functionality is exactly same in
clock.c. To accommodate this change in clock name #ifdef is used.

Following is the function in clock .c which uses #ifdef to accommodate
the different clock name in SoC's.

static unsigned long exynos_get_pwm_clk(void)
{
        struct exynos_clock *clk =
                (struct exynos_clock *)samsung_get_base_clock();
        unsigned long pclk, sclk;
        unsigned int sel;
        unsigned int ratio;

        if (s5p_get_cpu_rev() == 0) {
                /*
                 * CLK_SRC_{PERIL0 | PERIC0}
                 * PWM_SEL [27:24]
                 */
#ifdef CONFIG_EXYNOS5
                sel = readl(&clk->src_peric0);
#else
                sel = readl(&clk->src_peril0);
#endif
                sel = (sel >> 24) & 0xf;

                if (sel == 0x6)
                        sclk = get_pll_clk(MPLL);
                else if (sel == 0x7)
                        sclk = get_pll_clk(EPLL);
                else if (sel == 0x8)
                        sclk = get_pll_clk(VPLL);
                else
                        return 0;

                /*
                 * CLK_DIV_{PERIL3 | PERIC3}
                 * PWM_RATIO [3:0]
                 */
#ifdef CONFIG_EXYNOS5
                ratio = readl(&clk->div_peric3);
#else
                ratio = readl(&clk->div_peril3);
#endif
                ratio = ratio & 0xf;
        } else if (s5p_get_cpu_rev() == 1) {
                sclk = get_pll_clk(MPLL);
                ratio = 8;
        } else
                return 0;

        pclk = sclk / (ratio + 1);

        return pclk;
}

As listed above, the exynos_get_pwm_clk(() function is fully reusable
for both Exynos4 and Exynos5. The #ifdef was used to get around the
different clock names of Exynos4 and Exynos5.

Another option here could be, that the differing clock name
(src_peril0 for Exynos4 and src_peric0 for Exynos5) is resolved by
change the src_peric0 to src_peril0 for Exynos5, and clearly
commenting the reason for the deviation from the user manual. Would
this approach be acceptable ?

Thanks for your comments. Please let know your opinion about the
points listed in this email.


>
> like this,
>
> unsigned long get_arm_clk(void)
> {
>        if (cpu_is_s5pc110())
>                return s5pc110_get_arm_clk();
>        else
>                return s5pc100_get_arm_clk();
> }
>
> Thanks.
> Minkyu Kang
> --
> from. prom.
> www.promsoft.net
Wolfgang Denk Jan. 5, 2012, 11:32 a.m. | #8
Dear Chander Kashyap,

In message <CANuQgHHY8_6M1RivA6RawRY0pVrX5nnykxd_P+u340A0D4jRFA@mail.gmail.com> you wrote:
>
> > No need to reuse the code, if SoCs are different.
> > If need, please separate the functions.
> 
> Yes, though SoC's are different, the functionality in clock.c is
> similar. The only difference is the clock name in the clock structure
> for Exynos4 and Exynos5 but the functionality is exactly same in
> clock.c. To accommodate this change in clock name #ifdef is used.

If this is the only difference, then I suggest just to rename the
field in thesta structure.  Although it makes sense to follow the names
in the documentation, it is sometimes better tochose a more suitable
name - a comment in the header file should be sufficient to explain
the rename (and to provide an anchor in case something greps for the
name as used in the docs).

Maybe we can avoid both #ifdef's and code duplication this way?

Best regards,

Wolfgang Denk
Minkyu Kang Jan. 6, 2012, 1:40 a.m. | #9
Dear Chander Kashyap,

On 5 January 2012 19:31, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> Hi Minkyu Kang,
>
> On 5 January 2012 12:13, Minkyu Kang <promsoft@gmail.com> wrote:
>> Dear Chander Kashyap,
>>
>> On 27 December 2011 17:48, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>>>>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>>>>> >        scb9328         ARM920T (i.MXL)
>>>>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>>>> > index b101f96..88e2fc0 100644
>>>>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>>>>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>>>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>>>>> >
>>>>> >        if (s5p_get_cpu_rev() == 0) {
>>>>> >                /*
>>>>> > -                * CLK_SRC_PERIL0
>>>>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>>>>> >                 * PWM_SEL [27:24]
>>>>> >                 */
>>>>> > +#ifdef CONFIG_EXYNOS5
>>>>> > +               sel = readl(&clk->src_peric0);
>>>>> > +#else
>>>>> >                sel = readl(&clk->src_peril0);
>>>>> > +#endif
>>>>>
>>>>> NAK.
>>>>> We don't allow to using ifdef for separating SoCs.
>>>>> Please refer s5pc1xx case for solve it.
>>>>> This comment apply to this patch globally.
>>>>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>>>>
>>>> I have tried to reuse the code. It is possible to remove
>>>> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
>>>> Is it a acceptable solution? Or is it necessary to write SoC specific function
>>>> in clock.c as done in case of s5pc1xx/clock.c.
>>>>
>>>> Please Advice
>>> Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
>>> reuse the code in clock.c.
>>> What is the technical hindrance of not using ifdefs?
>>
>> No need to reuse the code, if SoCs are different.
>> If need, please separate the functions.
>
> Yes, though SoC's are different, the functionality in clock.c is
> similar. The only difference is the clock name in the clock structure
> for Exynos4 and Exynos5 but the functionality is exactly same in
> clock.c. To accommodate this change in clock name #ifdef is used.
>
> Following is the function in clock .c which uses #ifdef to accommodate
> the different clock name in SoC's.
>
> static unsigned long exynos_get_pwm_clk(void)
> {
>        struct exynos_clock *clk =
>                (struct exynos_clock *)samsung_get_base_clock();
>        unsigned long pclk, sclk;
>        unsigned int sel;
>        unsigned int ratio;
>
>        if (s5p_get_cpu_rev() == 0) {
>                /*
>                 * CLK_SRC_{PERIL0 | PERIC0}
>                 * PWM_SEL [27:24]
>                 */
> #ifdef CONFIG_EXYNOS5
>                sel = readl(&clk->src_peric0);
> #else
>                sel = readl(&clk->src_peril0);
> #endif
>                sel = (sel >> 24) & 0xf;
>
>                if (sel == 0x6)
>                        sclk = get_pll_clk(MPLL);
>                else if (sel == 0x7)
>                        sclk = get_pll_clk(EPLL);
>                else if (sel == 0x8)
>                        sclk = get_pll_clk(VPLL);
>                else
>                        return 0;
>
>                /*
>                 * CLK_DIV_{PERIL3 | PERIC3}
>                 * PWM_RATIO [3:0]
>                 */
> #ifdef CONFIG_EXYNOS5
>                ratio = readl(&clk->div_peric3);
> #else
>                ratio = readl(&clk->div_peril3);
> #endif
>                ratio = ratio & 0xf;
>        } else if (s5p_get_cpu_rev() == 1) {
>                sclk = get_pll_clk(MPLL);
>                ratio = 8;
>        } else
>                return 0;
>
>        pclk = sclk / (ratio + 1);
>
>        return pclk;
> }
>
> As listed above, the exynos_get_pwm_clk(() function is fully reusable
> for both Exynos4 and Exynos5. The #ifdef was used to get around the
> different clock names of Exynos4 and Exynos5.
>
> Another option here could be, that the differing clock name
> (src_peril0 for Exynos4 and src_peric0 for Exynos5) is resolved by
> change the src_peric0 to src_peril0 for Exynos5, and clearly
> commenting the reason for the deviation from the user manual. Would
> this approach be acceptable ?
>

Using same clock's name is acceptable.

But exynos4 clock structure and exynos5 clock structure are different.
I requested removing all ifdefs in your patch.
So, I will not allow such cases.

+#ifdef CONFIG_EXYNOS4
+#include<asm/arch/clock_exynos4.h>
+#elif defined CONFIG_EXYNOS5
+#include<asm/arch/clock_exynos5.h>
 #endif

Then, we should do like this,

        struct exynos4_clock *clk =
                (struct exynos4_clock *)samsung_get_base_clock();

        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();

how solve it?

And you should consider variation by cpu revision.
If Exynos5 revision1 is different from Exynos4 revision1, then?

Thanks.
Minkyu Kang.
Chander Kashyap Jan. 6, 2012, 12:48 p.m. | #10
Dear Wolfgang Denk,

On 5 January 2012 17:02, Wolfgang Denk <wd@denx.de> wrote:
> Dear Chander Kashyap,
>
> In message <CANuQgHHY8_6M1RivA6RawRY0pVrX5nnykxd_P+u340A0D4jRFA@mail.gmail.com> you wrote:
>>
>> > No need to reuse the code, if SoCs are different.
>> > If need, please separate the functions.
>>
>> Yes, though SoC's are different, the functionality in clock.c is
>> similar. The only difference is the clock name in the clock structure
>> for Exynos4 and Exynos5 but the functionality is exactly same in
>> clock.c. To accommodate this change in clock name #ifdef is used.
>
> If this is the only difference, then I suggest just to rename the
> field in thesta structure.  Although it makes sense to follow the names
> in the documentation, it is sometimes better tochose a more suitable
> name - a comment in the header file should be sufficient to explain
> the rename (and to provide an anchor in case something greps for the
> name as used in the docs).
>
> Maybe we can avoid both #ifdef's and code duplication this way?
Thanks for the suggestion.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
> What was sliced bread the greatest thing since?
Chander Kashyap Jan. 6, 2012, 12:50 p.m. | #11
Dear Minkyu Kang,

On 6 January 2012 07:10, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Chander Kashyap,
>
> On 5 January 2012 19:31, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>> Hi Minkyu Kang,
>>
>> On 5 January 2012 12:13, Minkyu Kang <promsoft@gmail.com> wrote:
>>> Dear Chander Kashyap,
>>>
>>> On 27 December 2011 17:48, Chander Kashyap <chander.kashyap@linaro.org> wrote:
>>>>>> >  Torsten Koschorrek <koschorrek@synertronixx.de>
>>>>>> >        scb9328         ARM920T (i.MXL)
>>>>>> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>>>>>> > index b101f96..88e2fc0 100644
>>>>>> > --- a/arch/arm/cpu/armv7/exynos/clock.c
>>>>>> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>>>>> > @@ -125,10 +125,14 @@ static unsigned long exynos_get_pwm_clk(void)
>>>>>> >
>>>>>> >        if (s5p_get_cpu_rev() == 0) {
>>>>>> >                /*
>>>>>> > -                * CLK_SRC_PERIL0
>>>>>> > +                * CLK_SRC_{PERIL0 | PERIC0}
>>>>>> >                 * PWM_SEL [27:24]
>>>>>> >                 */
>>>>>> > +#ifdef CONFIG_EXYNOS5
>>>>>> > +               sel = readl(&clk->src_peric0);
>>>>>> > +#else
>>>>>> >                sel = readl(&clk->src_peril0);
>>>>>> > +#endif
>>>>>>
>>>>>> NAK.
>>>>>> We don't allow to using ifdef for separating SoCs.
>>>>>> Please refer s5pc1xx case for solve it.
>>>>>> This comment apply to this patch globally.
>>>>>> Please remove '#ifdef CONFIG_EXYNOS5'.
>>>>>>
>>>>> I have tried to reuse the code. It is possible to remove
>>>>> #ifdef CONFIG_EXYNOS5' in clock.c with cpu_is_s5pcXXX check.
>>>>> Is it a acceptable solution? Or is it necessary to write SoC specific function
>>>>> in clock.c as done in case of s5pc1xx/clock.c.
>>>>>
>>>>> Please Advice
>>>> Removing CONFIG_EXYNOS5 and following s5pc1xx case will not allow to
>>>> reuse the code in clock.c.
>>>> What is the technical hindrance of not using ifdefs?
>>>
>>> No need to reuse the code, if SoCs are different.
>>> If need, please separate the functions.
>>
>> Yes, though SoC's are different, the functionality in clock.c is
>> similar. The only difference is the clock name in the clock structure
>> for Exynos4 and Exynos5 but the functionality is exactly same in
>> clock.c. To accommodate this change in clock name #ifdef is used.
>>
>> Following is the function in clock .c which uses #ifdef to accommodate
>> the different clock name in SoC's.
>>
>> static unsigned long exynos_get_pwm_clk(void)
>> {
>>        struct exynos_clock *clk =
>>                (struct exynos_clock *)samsung_get_base_clock();
>>        unsigned long pclk, sclk;
>>        unsigned int sel;
>>        unsigned int ratio;
>>
>>        if (s5p_get_cpu_rev() == 0) {
>>                /*
>>                 * CLK_SRC_{PERIL0 | PERIC0}
>>                 * PWM_SEL [27:24]
>>                 */
>> #ifdef CONFIG_EXYNOS5
>>                sel = readl(&clk->src_peric0);
>> #else
>>                sel = readl(&clk->src_peril0);
>> #endif
>>                sel = (sel >> 24) & 0xf;
>>
>>                if (sel == 0x6)
>>                        sclk = get_pll_clk(MPLL);
>>                else if (sel == 0x7)
>>                        sclk = get_pll_clk(EPLL);
>>                else if (sel == 0x8)
>>                        sclk = get_pll_clk(VPLL);
>>                else
>>                        return 0;
>>
>>                /*
>>                 * CLK_DIV_{PERIL3 | PERIC3}
>>                 * PWM_RATIO [3:0]
>>                 */
>> #ifdef CONFIG_EXYNOS5
>>                ratio = readl(&clk->div_peric3);
>> #else
>>                ratio = readl(&clk->div_peril3);
>> #endif
>>                ratio = ratio & 0xf;
>>        } else if (s5p_get_cpu_rev() == 1) {
>>                sclk = get_pll_clk(MPLL);
>>                ratio = 8;
>>        } else
>>                return 0;
>>
>>        pclk = sclk / (ratio + 1);
>>
>>        return pclk;
>> }
>>
>> As listed above, the exynos_get_pwm_clk(() function is fully reusable
>> for both Exynos4 and Exynos5. The #ifdef was used to get around the
>> different clock names of Exynos4 and Exynos5.
>>
>> Another option here could be, that the differing clock name
>> (src_peril0 for Exynos4 and src_peric0 for Exynos5) is resolved by
>> change the src_peric0 to src_peril0 for Exynos5, and clearly
>> commenting the reason for the deviation from the user manual. Would
>> this approach be acceptable ?
>>
>
> Using same clock's name is acceptable.
>
> But exynos4 clock structure and exynos5 clock structure are different.
> I requested removing all ifdefs in your patch.
> So, I will not allow such cases.
In that case S5PC1XX approach is suitable.
>
> +#ifdef CONFIG_EXYNOS4
> +#include<asm/arch/clock_exynos4.h>
> +#elif defined CONFIG_EXYNOS5
> +#include<asm/arch/clock_exynos5.h>
>  #endif
>
> Then, we should do like this,
>
>         struct exynos4_clock *clk =
>                 (struct exynos4_clock *)samsung_get_base_clock();
>
>         struct exynos5_clock *clk =
>                 (struct exynos5_clock *)samsung_get_base_clock();
>
> how solve it?
>
> And you should consider variation by cpu revision.
> If Exynos5 revision1 is different from Exynos4 revision1, then?
>
I will resend patche based on s5pc1xx approch.
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index a56ca10..abf88be 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -704,6 +704,7 @@  Chander Kashyap <k.chander@samsung.com>
 
 	origen			ARM ARMV7 (EXYNOS4210 SoC)
 	SMDKV310		ARM ARMV7 (EXYNOS4210 SoC)
+	SMDK5250		ARM ARMV7 (EXYNOS5250 SoC)
 
 Torsten Koschorrek <koschorrek@synertronixx.de>
 	scb9328		ARM920T (i.MXL)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b101f96..88e2fc0 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -125,10 +125,14 @@  static unsigned long exynos_get_pwm_clk(void)
 
 	if (s5p_get_cpu_rev() == 0) {
 		/*
-		 * CLK_SRC_PERIL0
+		 * CLK_SRC_{PERIL0 | PERIC0}
 		 * PWM_SEL [27:24]
 		 */
+#ifdef CONFIG_EXYNOS5
+		sel = readl(&clk->src_peric0);
+#else
 		sel = readl(&clk->src_peril0);
+#endif
 		sel = (sel >> 24) & 0xf;
 
 		if (sel == 0x6)
@@ -141,10 +145,14 @@  static unsigned long exynos_get_pwm_clk(void)
 			return 0;
 
 		/*
-		 * CLK_DIV_PERIL3
+		 * CLK_DIV_{PERIL3 | PERIC3}
 		 * PWM_RATIO [3:0]
 		 */
+#ifdef CONFIG_EXYNOS5
+		ratio = readl(&clk->div_peric3);
+#else
 		ratio = readl(&clk->div_peril3);
+#endif
 		ratio = ratio & 0xf;
 	} else if (s5p_get_cpu_rev() == 1) {
 		sclk = get_pll_clk(MPLL);
@@ -167,7 +175,7 @@  static unsigned long exynos_get_uart_clk(int dev_index)
 	unsigned int ratio;
 
 	/*
-	 * CLK_SRC_PERIL0
+	 * CLK_SRC_{PERIL0 | PERIC0}
 	 * UART0_SEL [3:0]
 	 * UART1_SEL [7:4]
 	 * UART2_SEL [8:11]
@@ -175,7 +183,11 @@  static unsigned long exynos_get_uart_clk(int dev_index)
 	 * UART4_SEL [16:19]
 	 * UART5_SEL [23:20]
 	 */
+#ifdef CONFIG_EXYNOS5
+	sel = readl(&clk->src_peric0);
+#else
 	sel = readl(&clk->src_peril0);
+#endif
 	sel = (sel >> (dev_index << 2)) & 0xf;
 
 	if (sel == 0x6)
@@ -188,7 +200,7 @@  static unsigned long exynos_get_uart_clk(int dev_index)
 		return 0;
 
 	/*
-	 * CLK_DIV_PERIL0
+	 * CLK_DIV_{PERIL0 | PERIC0}
 	 * UART0_RATIO [3:0]
 	 * UART1_RATIO [7:4]
 	 * UART2_RATIO [8:11]
@@ -196,7 +208,11 @@  static unsigned long exynos_get_uart_clk(int dev_index)
 	 * UART4_RATIO [16:19]
 	 * UART5_RATIO [23:20]
 	 */
+#ifdef CONFIG_EXYNOS5
+	ratio = readl(&clk->div_peric0);
+#else
 	ratio = readl(&clk->div_peril0);
+#endif
 	ratio = (ratio >> (dev_index << 2)) & 0xf;
 
 	uclk = sclk / (ratio + 1);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index ecd0cb1..bc790cc 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -22,234 +22,10 @@ 
 #ifndef __ASM_ARM_ARCH_CLOCK_H_
 #define __ASM_ARM_ARCH_CLOCK_H_
 
-#ifndef __ASSEMBLY__
-struct exynos_clock {
-	unsigned char	res1[0x4200];
-	unsigned int	src_leftbus;
-	unsigned char	res2[0x1fc];
-	unsigned int	mux_stat_leftbus;
-	unsigned char	res4[0xfc];
-	unsigned int	div_leftbus;
-	unsigned char	res5[0xfc];
-	unsigned int	div_stat_leftbus;
-	unsigned char	res6[0x1fc];
-	unsigned int	gate_ip_leftbus;
-	unsigned char	res7[0x1fc];
-	unsigned int	clkout_leftbus;
-	unsigned int	clkout_leftbus_div_stat;
-	unsigned char	res8[0x37f8];
-	unsigned int	src_rightbus;
-	unsigned char	res9[0x1fc];
-	unsigned int	mux_stat_rightbus;
-	unsigned char	res10[0xfc];
-	unsigned int	div_rightbus;
-	unsigned char	res11[0xfc];
-	unsigned int	div_stat_rightbus;
-	unsigned char	res12[0x1fc];
-	unsigned int	gate_ip_rightbus;
-	unsigned char	res13[0x1fc];
-	unsigned int	clkout_rightbus;
-	unsigned int	clkout_rightbus_div_stat;
-	unsigned char	res14[0x3608];
-	unsigned int	epll_lock;
-	unsigned char	res15[0xc];
-	unsigned int	vpll_lock;
-	unsigned char	res16[0xec];
-	unsigned int	epll_con0;
-	unsigned int	epll_con1;
-	unsigned char	res17[0x8];
-	unsigned int	vpll_con0;
-	unsigned int	vpll_con1;
-	unsigned char	res18[0xe8];
-	unsigned int	src_top0;
-	unsigned int	src_top1;
-	unsigned char	res19[0x8];
-	unsigned int	src_cam;
-	unsigned int	src_tv;
-	unsigned int	src_mfc;
-	unsigned int	src_g3d;
-	unsigned int	src_image;
-	unsigned int	src_lcd0;
-	unsigned int	src_lcd1;
-	unsigned int	src_maudio;
-	unsigned int	src_fsys;
-	unsigned char	res20[0xc];
-	unsigned int	src_peril0;
-	unsigned int	src_peril1;
-	unsigned char	res21[0xb8];
-	unsigned int	src_mask_top;
-	unsigned char	res22[0xc];
-	unsigned int	src_mask_cam;
-	unsigned int	src_mask_tv;
-	unsigned char	res23[0xc];
-	unsigned int	src_mask_lcd0;
-	unsigned int	src_mask_lcd1;
-	unsigned int	src_mask_maudio;
-	unsigned int	src_mask_fsys;
-	unsigned char	res24[0xc];
-	unsigned int	src_mask_peril0;
-	unsigned int	src_mask_peril1;
-	unsigned char	res25[0xb8];
-	unsigned int	mux_stat_top;
-	unsigned char	res26[0x14];
-	unsigned int	mux_stat_mfc;
-	unsigned int	mux_stat_g3d;
-	unsigned int	mux_stat_image;
-	unsigned char	res27[0xdc];
-	unsigned int	div_top;
-	unsigned char	res28[0xc];
-	unsigned int	div_cam;
-	unsigned int	div_tv;
-	unsigned int	div_mfc;
-	unsigned int	div_g3d;
-	unsigned int	div_image;
-	unsigned int	div_lcd0;
-	unsigned int	div_lcd1;
-	unsigned int	div_maudio;
-	unsigned int	div_fsys0;
-	unsigned int	div_fsys1;
-	unsigned int	div_fsys2;
-	unsigned int	div_fsys3;
-	unsigned int	div_peril0;
-	unsigned int	div_peril1;
-	unsigned int	div_peril2;
-	unsigned int	div_peril3;
-	unsigned int	div_peril4;
-	unsigned int	div_peril5;
-	unsigned char	res29[0x18];
-	unsigned int	div2_ratio;
-	unsigned char	res30[0x8c];
-	unsigned int	div_stat_top;
-	unsigned char	res31[0xc];
-	unsigned int	div_stat_cam;
-	unsigned int	div_stat_tv;
-	unsigned int	div_stat_mfc;
-	unsigned int	div_stat_g3d;
-	unsigned int	div_stat_image;
-	unsigned int	div_stat_lcd0;
-	unsigned int	div_stat_lcd1;
-	unsigned int	div_stat_maudio;
-	unsigned int	div_stat_fsys0;
-	unsigned int	div_stat_fsys1;
-	unsigned int	div_stat_fsys2;
-	unsigned int	div_stat_fsys3;
-	unsigned int	div_stat_peril0;
-	unsigned int	div_stat_peril1;
-	unsigned int	div_stat_peril2;
-	unsigned int	div_stat_peril3;
-	unsigned int	div_stat_peril4;
-	unsigned int	div_stat_peril5;
-	unsigned char	res32[0x18];
-	unsigned int	div2_stat;
-	unsigned char	res33[0x29c];
-	unsigned int	gate_ip_cam;
-	unsigned int	gate_ip_tv;
-	unsigned int	gate_ip_mfc;
-	unsigned int	gate_ip_g3d;
-	unsigned int	gate_ip_image;
-	unsigned int	gate_ip_lcd0;
-	unsigned int	gate_ip_lcd1;
-	unsigned char	res34[0x4];
-	unsigned int	gate_ip_fsys;
-	unsigned char	res35[0x8];
-	unsigned int	gate_ip_gps;
-	unsigned int	gate_ip_peril;
-	unsigned char	res36[0xc];
-	unsigned int	gate_ip_perir;
-	unsigned char	res37[0xc];
-	unsigned int	gate_block;
-	unsigned char	res38[0x8c];
-	unsigned int	clkout_cmu_top;
-	unsigned int	clkout_cmu_top_div_stat;
-	unsigned char	res39[0x37f8];
-	unsigned int	src_dmc;
-	unsigned char	res40[0xfc];
-	unsigned int	src_mask_dmc;
-	unsigned char	res41[0xfc];
-	unsigned int	mux_stat_dmc;
-	unsigned char	res42[0xfc];
-	unsigned int	div_dmc0;
-	unsigned int	div_dmc1;
-	unsigned char	res43[0xf8];
-	unsigned int	div_stat_dmc0;
-	unsigned int	div_stat_dmc1;
-	unsigned char	res44[0x2f8];
-	unsigned int	gate_ip_dmc;
-	unsigned char	res45[0xfc];
-	unsigned int	clkout_cmu_dmc;
-	unsigned int	clkout_cmu_dmc_div_stat;
-	unsigned char	res46[0x5f8];
-	unsigned int	dcgidx_map0;
-	unsigned int	dcgidx_map1;
-	unsigned int	dcgidx_map2;
-	unsigned char	res47[0x14];
-	unsigned int	dcgperf_map0;
-	unsigned int	dcgperf_map1;
-	unsigned char	res48[0x18];
-	unsigned int	dvcidx_map;
-	unsigned char	res49[0x1c];
-	unsigned int	freq_cpu;
-	unsigned int	freq_dpm;
-	unsigned char	res50[0x18];
-	unsigned int	dvsemclk_en;
-	unsigned int	maxperf;
-	unsigned char	res51[0x2f78];
-	unsigned int	apll_lock;
-	unsigned char	res52[0x4];
-	unsigned int	mpll_lock;
-	unsigned char	res53[0xf4];
-	unsigned int	apll_con0;
-	unsigned int	apll_con1;
-	unsigned int	mpll_con0;
-	unsigned int	mpll_con1;
-	unsigned char	res54[0xf0];
-	unsigned int	src_cpu;
-	unsigned char	res55[0x1fc];
-	unsigned int	mux_stat_cpu;
-	unsigned char	res56[0xfc];
-	unsigned int	div_cpu0;
-	unsigned int	div_cpu1;
-	unsigned char	res57[0xf8];
-	unsigned int	div_stat_cpu0;
-	unsigned int	div_stat_cpu1;
-	unsigned char	res58[0x3f8];
-	unsigned int	clkout_cmu_cpu;
-	unsigned int	clkout_cmu_cpu_div_stat;
-	unsigned char	res59[0x5f8];
-	unsigned int	armclk_stopctrl;
-	unsigned int	atclk_stopctrl;
-	unsigned char	res60[0x8];
-	unsigned int	parityfail_status;
-	unsigned int	parityfail_clear;
-	unsigned char	res61[0xe8];
-	unsigned int	apll_con0_l8;
-	unsigned int	apll_con0_l7;
-	unsigned int	apll_con0_l6;
-	unsigned int	apll_con0_l5;
-	unsigned int	apll_con0_l4;
-	unsigned int	apll_con0_l3;
-	unsigned int	apll_con0_l2;
-	unsigned int	apll_con0_l1;
-	unsigned int	iem_control;
-	unsigned char	res62[0xdc];
-	unsigned int	apll_con1_l8;
-	unsigned int	apll_con1_l7;
-	unsigned int	apll_con1_l6;
-	unsigned int	apll_con1_l5;
-	unsigned int	apll_con1_l4;
-	unsigned int	apll_con1_l3;
-	unsigned int	apll_con1_l2;
-	unsigned int	apll_con1_l1;
-	unsigned char	res63[0xe0];
-	unsigned int	div_iem_l8;
-	unsigned int	div_iem_l7;
-	unsigned int	div_iem_l6;
-	unsigned int	div_iem_l5;
-	unsigned int	div_iem_l4;
-	unsigned int	div_iem_l3;
-	unsigned int	div_iem_l2;
-	unsigned int	div_iem_l1;
-};
+#ifdef CONFIG_EXYNOS4
+#include<asm/arch/clock_exynos4.h>
+#elif defined CONFIG_EXYNOS5
+#include<asm/arch/clock_exynos5.h>
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/clock_exynos4.h b/arch/arm/include/asm/arch-exynos/clock_exynos4.h
new file mode 100644
index 0000000..b3f42d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/clock_exynos4.h
@@ -0,0 +1,255 @@ 
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_EXYNOS4_H_
+#define __ASM_ARM_ARCH_CLOCK_EXYNOS4_H_
+
+#ifndef __ASSEMBLY__
+struct exynos_clock {
+	unsigned char	res1[0x4200];
+	unsigned int	src_leftbus;
+	unsigned char	res2[0x1fc];
+	unsigned int	mux_stat_leftbus;
+	unsigned char	res4[0xfc];
+	unsigned int	div_leftbus;
+	unsigned char	res5[0xfc];
+	unsigned int	div_stat_leftbus;
+	unsigned char	res6[0x1fc];
+	unsigned int	gate_ip_leftbus;
+	unsigned char	res7[0x1fc];
+	unsigned int	clkout_leftbus;
+	unsigned int	clkout_leftbus_div_stat;
+	unsigned char	res8[0x37f8];
+	unsigned int	src_rightbus;
+	unsigned char	res9[0x1fc];
+	unsigned int	mux_stat_rightbus;
+	unsigned char	res10[0xfc];
+	unsigned int	div_rightbus;
+	unsigned char	res11[0xfc];
+	unsigned int	div_stat_rightbus;
+	unsigned char	res12[0x1fc];
+	unsigned int	gate_ip_rightbus;
+	unsigned char	res13[0x1fc];
+	unsigned int	clkout_rightbus;
+	unsigned int	clkout_rightbus_div_stat;
+	unsigned char	res14[0x3608];
+	unsigned int	epll_lock;
+	unsigned char	res15[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res16[0xec];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned char	res17[0x8];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned char	res18[0xe8];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned char	res19[0x8];
+	unsigned int	src_cam;
+	unsigned int	src_tv;
+	unsigned int	src_mfc;
+	unsigned int	src_g3d;
+	unsigned int	src_image;
+	unsigned int	src_lcd0;
+	unsigned int	src_lcd1;
+	unsigned int	src_maudio;
+	unsigned int	src_fsys;
+	unsigned char	res20[0xc];
+	unsigned int	src_peril0;
+	unsigned int	src_peril1;
+	unsigned char	res21[0xb8];
+	unsigned int	src_mask_top;
+	unsigned char	res22[0xc];
+	unsigned int	src_mask_cam;
+	unsigned int	src_mask_tv;
+	unsigned char	res23[0xc];
+	unsigned int	src_mask_lcd0;
+	unsigned int	src_mask_lcd1;
+	unsigned int	src_mask_maudio;
+	unsigned int	src_mask_fsys;
+	unsigned char	res24[0xc];
+	unsigned int	src_mask_peril0;
+	unsigned int	src_mask_peril1;
+	unsigned char	res25[0xb8];
+	unsigned int	mux_stat_top;
+	unsigned char	res26[0x14];
+	unsigned int	mux_stat_mfc;
+	unsigned int	mux_stat_g3d;
+	unsigned int	mux_stat_image;
+	unsigned char	res27[0xdc];
+	unsigned int	div_top;
+	unsigned char	res28[0xc];
+	unsigned int	div_cam;
+	unsigned int	div_tv;
+	unsigned int	div_mfc;
+	unsigned int	div_g3d;
+	unsigned int	div_image;
+	unsigned int	div_lcd0;
+	unsigned int	div_lcd1;
+	unsigned int	div_maudio;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peril0;
+	unsigned int	div_peril1;
+	unsigned int	div_peril2;
+	unsigned int	div_peril3;
+	unsigned int	div_peril4;
+	unsigned int	div_peril5;
+	unsigned char	res29[0x18];
+	unsigned int	div2_ratio;
+	unsigned char	res30[0x8c];
+	unsigned int	div_stat_top;
+	unsigned char	res31[0xc];
+	unsigned int	div_stat_cam;
+	unsigned int	div_stat_tv;
+	unsigned int	div_stat_mfc;
+	unsigned int	div_stat_g3d;
+	unsigned int	div_stat_image;
+	unsigned int	div_stat_lcd0;
+	unsigned int	div_stat_lcd1;
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peril0;
+	unsigned int	div_stat_peril1;
+	unsigned int	div_stat_peril2;
+	unsigned int	div_stat_peril3;
+	unsigned int	div_stat_peril4;
+	unsigned int	div_stat_peril5;
+	unsigned char	res32[0x18];
+	unsigned int	div2_stat;
+	unsigned char	res33[0x29c];
+	unsigned int	gate_ip_cam;
+	unsigned int	gate_ip_tv;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_image;
+	unsigned int	gate_ip_lcd0;
+	unsigned int	gate_ip_lcd1;
+	unsigned char	res34[0x4];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res35[0x8];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peril;
+	unsigned char	res36[0xc];
+	unsigned int	gate_ip_perir;
+	unsigned char	res37[0xc];
+	unsigned int	gate_block;
+	unsigned char	res38[0x8c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res39[0x37f8];
+	unsigned int	src_dmc;
+	unsigned char	res40[0xfc];
+	unsigned int	src_mask_dmc;
+	unsigned char	res41[0xfc];
+	unsigned int	mux_stat_dmc;
+	unsigned char	res42[0xfc];
+	unsigned int	div_dmc0;
+	unsigned int	div_dmc1;
+	unsigned char	res43[0xf8];
+	unsigned int	div_stat_dmc0;
+	unsigned int	div_stat_dmc1;
+	unsigned char	res44[0x2f8];
+	unsigned int	gate_ip_dmc;
+	unsigned char	res45[0xfc];
+	unsigned int	clkout_cmu_dmc;
+	unsigned int	clkout_cmu_dmc_div_stat;
+	unsigned char	res46[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res47[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res48[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res49[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res50[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res51[0x2f78];
+	unsigned int	apll_lock;
+	unsigned char	res52[0x4];
+	unsigned int	mpll_lock;
+	unsigned char	res53[0xf4];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res54[0xf0];
+	unsigned int	src_cpu;
+	unsigned char	res55[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res56[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res57[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res58[0x3f8];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res59[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res60[0x8];
+	unsigned int	parityfail_status;
+	unsigned int	parityfail_clear;
+	unsigned char	res61[0xe8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res62[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res63[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/clock_exynos5.h b/arch/arm/include/asm/arch-exynos/clock_exynos5.h
new file mode 100644
index 0000000..ba04609
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/clock_exynos5.h
@@ -0,0 +1,352 @@ 
+/*
+ * (C) Copyright 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_EXYNOS5_H_
+#define __ASM_ARM_ARCH_CLOCK_EXYNOS5_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_clock {
+	unsigned int	apll_lock;
+	unsigned char	res1[0xfc];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res2[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res3[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res4[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res5[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res6[0x1f8];
+	unsigned int	gate_sclk_cpu;
+	unsigned char	res7[0x1fc];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res8[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res9[0x8];
+	unsigned int	parityfail_status;
+	unsigned int	parityfail_clear;
+	unsigned char	res10[0x8];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctr2;
+	unsigned char	res11[0xd8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res12[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res13[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+	unsigned char	res14[0x2ce0];
+	unsigned int	mpll_lock;
+	unsigned char	res15[0xfc];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res16[0xf8];
+	unsigned int	src_core0;
+	unsigned int	src_core1;
+	unsigned char	res17[0xf8];
+	unsigned int	src_mask_core;
+	unsigned char	res18[0x100];
+	unsigned int	mux_stat_core1;
+	unsigned char	res19[0xf8];
+	unsigned int	div_core0;
+	unsigned int	div_core1;
+	unsigned char	res20[0xf8];
+	unsigned int	div_stat_core0;
+	unsigned int	div_stat_core1;
+	unsigned char	res21[0x2f8];
+	unsigned int	gate_ip_core;
+	unsigned char	res22[0xfc];
+	unsigned int	clkout_cmu_core;
+	unsigned int	clkout_cmu_core_div_stat;
+	unsigned char	res23[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res24[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res25[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res26[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res27[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res28[0x3478];
+	unsigned int	div_acp;
+	unsigned char	res29[0xfc];
+	unsigned int	div_stat_acp;
+	unsigned char	res30[0x1fc];
+	unsigned int	gate_ip_acp;
+	unsigned char	res31[0x1fc];
+	unsigned int	clkout_cmu_acp;
+	unsigned int	clkout_cmu_acp_div_stat;
+	unsigned char	res32[0x38f8];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned int	div_isp2;
+	unsigned char	res33[0xf4];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned int	div_stat_isp2;
+	unsigned char	res34[0x3f4];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res35[0xf8];
+	unsigned int	gate_sclk_isp;
+	unsigned char	res36[0xc];
+	unsigned int	mcuisp_pwr_ctrl;
+	unsigned char	res37[0xec];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res38[0x3618];
+	unsigned int	cpll_lock;
+	unsigned char	res39[0xc];
+	unsigned int	epll_lock;
+	unsigned char	res40[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res41[0xdc];
+	unsigned int	cpll_con0;
+	unsigned int	cpll_con1;
+	unsigned char	res42[0x8];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res43[0x4];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned int	vpll_con8;
+	unsigned char	res44[0xc4];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned int	src_top2;
+	unsigned int	src_top3;
+	unsigned int	src_gscl;
+	unsigned int	src_disp0_0;
+	unsigned int	src_disp0_1;
+	unsigned int	src_disp1_0;
+	unsigned int	src_disp1_1;
+	unsigned char	res46[0xc];
+	unsigned int	src_mau;
+	unsigned int	src_fsys;
+	unsigned char	res47[0x8];
+	unsigned int	src_peric0;
+	unsigned int	src_peric1;
+	unsigned char	res48[0x18];
+	unsigned int	sclk_src_isp;
+	unsigned char	res49[0x9c];
+	unsigned int	src_mask_top;
+	unsigned char	res50[0xc];
+	unsigned int	src_mask_gscl;
+	unsigned int	src_mayk_disp0_0;
+	unsigned int	src_mask_disp0_1;
+	unsigned int	src_mask_disp1_0;
+	unsigned int	src_mask_disp1_1;
+	unsigned int	src_mask_maudio;
+	unsigned char	res52[0x8];
+	unsigned int	src_mask_fsys;
+	unsigned char	res53[0xc];
+	unsigned int	src_mask_peric0;
+	unsigned int	src_mask_peric1;
+	unsigned char	res54[0x18];
+	unsigned int	src_mask_isp;
+	unsigned char	res55[0x9c];
+	unsigned int	mux_stat_top0;
+	unsigned int	mux_stat_top1;
+	unsigned int	mux_stat_top2;
+	unsigned int	mux_stat_top3;
+	unsigned char	res56[0xf0];
+	unsigned int	div_top0;
+	unsigned int	div_top1;
+	unsigned char	res57[0x8];
+	unsigned int	div_gscl;
+	unsigned int	div_disp0_0;
+	unsigned int	div_disp0_1;
+	unsigned int	div_disp1_0;
+	unsigned int	div_disp1_1;
+	unsigned char	res59[0x8];
+	unsigned int	div_gen;
+	unsigned char	res60[0x4];
+	unsigned int	div_mau;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peric0;
+	unsigned int	div_peric1;
+	unsigned int	div_peric2;
+	unsigned int	div_peric3;
+	unsigned int	div_peric4;
+	unsigned int	div_peric5;
+	unsigned char	res61[0x10];
+	unsigned int	sclk_div_isp;
+	unsigned char	res62[0xc];
+	unsigned int	div2_ratio0;
+	unsigned int	div2_ratio1;
+	unsigned char	res63[0x8];
+	unsigned int	div4_ratio;
+	unsigned char	res64[0x6c];
+	unsigned int	div_stat_top0;
+	unsigned int	div_stat_top1;
+	unsigned char	res65[0x8];
+	unsigned int	div_stat_gscl;
+	unsigned int	div_stat_disp0_0;
+	unsigned int	div_stat_disp0_1;
+	unsigned int	div_stat_disp1_0;
+	unsigned int	div_stat_disp1_1;
+	unsigned char	res67[0x8];
+	unsigned int	div_stat_gen;
+	unsigned char	res68[0x4];
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peric0;
+	unsigned int	div_stat_peric1;
+	unsigned int	div_stat_peric2;
+	unsigned int	div_stat_peric3;
+	unsigned int	div_stat_peric4;
+	unsigned int	div_stat_peric5;
+	unsigned char	res69[0x10];
+	unsigned int	sclk_div_stat_isp;
+	unsigned char	res70[0xc];
+	unsigned int	div2_stat0;
+	unsigned int	div2_stat1;
+	unsigned char	res71[0x8];
+	unsigned int	div4_stat;
+	unsigned char	res72[0x180];
+	unsigned int	gate_top_sclk_disp0;
+	unsigned int	gate_top_sclk_disp1;
+	unsigned int	gate_top_sclk_gen;
+	unsigned char	res74[0xc];
+	unsigned int	gate_top_sclk_mau;
+	unsigned int	gate_top_sclk_fsys;
+	unsigned char	res75[0xc];
+	unsigned int	gate_top_sclk_peric;
+	unsigned char	res76[0x1c];
+	unsigned int	gate_top_sclk_isp;
+	unsigned char	res77[0xac];
+	unsigned int	gate_ip_gscl;
+	unsigned int	gate_ip_disp0;
+	unsigned int	gate_ip_disp1;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_gen;
+	unsigned char	res79[0xc];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res80[0x4];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peric;
+	unsigned char	res81[0xc];
+	unsigned int	gate_ip_peris;
+	unsigned char	res82[0x1c];
+	unsigned int	gate_block;
+	unsigned char	res83[0x7c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res84[0x37f8];
+	unsigned int	src_lex;
+	unsigned char	res85[0x2fc];
+	unsigned int	div_lex;
+	unsigned char	res86[0xfc];
+	unsigned int	div_stat_lex;
+	unsigned char	res87[0x1fc];
+	unsigned int	gate_ip_lex;
+	unsigned char	res88[0x1fc];
+	unsigned int	clkout_cmu_lex;
+	unsigned int	clkout_cmu_lex_div_stat;
+	unsigned char	res89[0x3af8];
+	unsigned int	div_r0x;
+	unsigned char	res90[0xfc];
+	unsigned int	div_stat_r0x;
+	unsigned char	res91[0x1fc];
+	unsigned int	gate_ip_r0x;
+	unsigned char	res92[0x1fc];
+	unsigned int	clkout_cmu_r0x;
+	unsigned int	clkout_cmu_r0x_div_stat;
+	unsigned char	res94[0x3af8];
+	unsigned int	div_r1x;
+	unsigned char	res95[0xfc];
+	unsigned int	div_stat_r1x;
+	unsigned char	res96[0x1fc];
+	unsigned int	gate_ip_r1x;
+	unsigned char	res97[0x1fc];
+	unsigned int	clkout_cmu_r1x;
+	unsigned int	clkout_cmu_r1x_div_stat;
+	unsigned char	res98[0x3608];
+	unsigned int	bpll_lock;
+	unsigned char	res99[0xfc];
+	unsigned int	bpll_con0;
+	unsigned int	bpll_con1;
+	unsigned char	res100[0xe8];
+	unsigned int	src_cdrex;
+	unsigned char	res101[0x1fc];
+	unsigned int	mux_stat_cdrex;
+	unsigned char	res102[0xfc];
+	unsigned int	div_cdrex;
+	unsigned int	div_cdrex2;
+	unsigned char	res103[0xf8];
+	unsigned int	div_stat_cdrex;
+	unsigned char	res104[0x2fc];
+	unsigned int	gate_ip_cdrex;
+	unsigned char	res105[0xc];
+	unsigned int	c2c_monitor;
+	unsigned int	dmc_pwr_ctrl;
+	unsigned char	res106[0x4];
+	unsigned int	drex2_pause;
+	unsigned char	res107[0xe0];
+	unsigned int	clkout_cmu_cdrex;
+	unsigned int	clkout_cmu_cdrex_div_stat;
+	unsigned char	res108[0x8];
+	unsigned int	lpddr3phy_ctrl;
+	unsigned char	res109[0xf5f8];
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 6d97b99..08f7191 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -19,34 +19,14 @@ 
  *
  */
 
-#ifndef _EXYNOS4_CPU_H
-#define _EXYNOS4_CPU_H
+#ifndef _EXYNOS_CPU_H
+#define _EXYNOS_CPU_H
 
-#define EXYNOS4_ADDR_BASE		0x10000000
-
-/* EXYNOS4 */
-#define EXYNOS4_GPIO_PART3_BASE		0x03860000
-#define EXYNOS4_PRO_ID			0x10000000
-#define EXYNOS4_POWER_BASE		0x10020000
-#define EXYNOS4_SWRESET			0x10020400
-#define EXYNOS4_CLOCK_BASE		0x10030000
-#define EXYNOS4_SYSTIMER_BASE		0x10050000
-#define EXYNOS4_WATCHDOG_BASE		0x10060000
-#define EXYNOS4_MIU_BASE		0x10600000
-#define EXYNOS4_DMC0_BASE		0x10400000
-#define EXYNOS4_DMC1_BASE		0x10410000
-#define EXYNOS4_GPIO_PART2_BASE		0x11000000
-#define EXYNOS4_GPIO_PART1_BASE		0x11400000
-#define EXYNOS4_FIMD_BASE		0x11C00000
-#define EXYNOS4_USBOTG_BASE		0x12480000
-#define EXYNOS4_MMC_BASE		0x12510000
-#define EXYNOS4_SROMC_BASE		0x12570000
-#define EXYNOS4_USBPHY_BASE		0x125B0000
-#define EXYNOS4_UART_BASE		0x13800000
-#define EXYNOS4_ADC_BASE		0x13910000
-#define EXYNOS4_PWMTIMER_BASE		0x139D0000
-#define EXYNOS4_MODEM_BASE		0x13A00000
-#define EXYNOS4_USBPHY_CONTROL          0x10020704
+#ifdef CONFIG_EXYNOS4
+#include <asm/arch/cpu_exynos4.h>
+#elif defined CONFIG_EXYNOS5
+#include <asm/arch/cpu_exynos5.h>
+#endif
 
 #ifndef __ASSEMBLY__
 #include <asm/io.h>
@@ -61,7 +41,11 @@  static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
+#ifdef CONFIG_EXYNOS4
 	s5p_cpu_id = readl(EXYNOS4_PRO_ID);
+#elif defined CONFIG_EXYNOS5
+	s5p_cpu_id = readl(EXYNOS5_PRO_ID);
+#endif
 	s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
 
 	/*
@@ -71,9 +55,8 @@  static inline void s5p_set_cpu_id(void)
 	if (s5p_cpu_id == 0xC200) {
 		s5p_cpu_id |= 0x10;
 		s5p_cpu_rev = 0;
-	} else if (s5p_cpu_id == 0xC210) {
+	} else if (s5p_cpu_id == 0xC210)
 		s5p_cpu_rev = 1;
-	}
 }
 
 #define IS_SAMSUNG_TYPE(type, id)			\
@@ -82,8 +65,13 @@  static inline int cpu_is_##type(void)			\
 	return s5p_cpu_id == id ? 1 : 0;		\
 }
 
+#ifdef CONFIG_EXYNOS4
 IS_SAMSUNG_TYPE(exynos4, 0xc210)
+#elif defined CONFIG_EXYNOS5
+IS_SAMSUNG_TYPE(exynos5, 0xc520)
+#endif
 
+#ifdef CONFIG_EXYNOS4
 #define SAMSUNG_BASE(device, base)				\
 static inline unsigned int samsung_get_base_##device(void)	\
 {								\
@@ -92,23 +80,36 @@  static inline unsigned int samsung_get_base_##device(void)	\
 	else							\
 		return 0;					\
 }
+#elif defined CONFIG_EXYNOS5
+#define SAMSUNG_BASE(device, base)				\
+static inline unsigned int samsung_get_base_##device(void)	\
+{								\
+	if (cpu_is_exynos5())					\
+		return EXYNOS5_##base;				\
+	else							\
+		return 0;					\
+}
+#endif
 
-SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
-SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
-SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
 SAMSUNG_BASE(pro_id, PRO_ID)
 SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(modem, MODEM_BASE)
 SAMSUNG_BASE(sromc, SROMC_BASE)
 SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+
+#ifdef CONFIG_EXYNOS4
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(modem, MODEM_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
-SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+#endif
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/cpu_exynos4.h b/arch/arm/include/asm/arch-exynos/cpu_exynos4.h
new file mode 100644
index 0000000..3b46f9d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/cpu_exynos4.h
@@ -0,0 +1,51 @@ 
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS4_CPU_H
+#define _EXYNOS4_CPU_H
+
+#define EXYNOS4_ADDR_BASE		0x10000000
+
+/* EXYNOS4 */
+#define EXYNOS4_GPIO_PART3_BASE		0x03860000
+#define EXYNOS4_PRO_ID			0x10000000
+#define EXYNOS4_POWER_BASE		0x10020000
+#define EXYNOS4_SWRESET			0x10020400
+#define EXYNOS4_CLOCK_BASE		0x10030000
+#define EXYNOS4_SYSTIMER_BASE		0x10050000
+#define EXYNOS4_WATCHDOG_BASE		0x10060000
+#define EXYNOS4_MIU_BASE		0x10600000
+#define EXYNOS4_DMC0_BASE		0x10400000
+#define EXYNOS4_DMC1_BASE		0x10410000
+#define EXYNOS4_GPIO_PART2_BASE		0x11000000
+#define EXYNOS4_GPIO_PART1_BASE		0x11400000
+#define EXYNOS4_FIMD_BASE		0x11C00000
+#define EXYNOS4_USBOTG_BASE		0x12480000
+#define EXYNOS4_MMC_BASE		0x12510000
+#define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USBPHY_BASE		0x125B0000
+#define EXYNOS4_UART_BASE		0x13800000
+#define EXYNOS4_ADC_BASE		0x13910000
+#define EXYNOS4_PWMTIMER_BASE		0x139D0000
+#define EXYNOS4_MODEM_BASE		0x13A00000
+#define EXYNOS4_USBPHY_CONTROL		0x10020704
+
+#endif	/* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/cpu_exynos5.h b/arch/arm/include/asm/arch-exynos/cpu_exynos5.h
new file mode 100644
index 0000000..f758e5d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/cpu_exynos5.h
@@ -0,0 +1,39 @@ 
+/*
+ * (C) Copyright 2011 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS5_CPU_H
+#define _EXYNOS5_CPU_H
+
+/* EXYNOS5 */
+#define EXYNOS5_PRO_ID			0x10000000
+#define EXYNOS5_CLOCK_BASE		0x10010000
+#define EXYNOS5_POWER_BASE		0x10040000
+#define EXYNOS5_SWRESET			0x10040400
+#define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_WATCHDOG_BASE		0x101D0000
+#define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_MMC_BASE		0x12200000
+#define EXYNOS5_SROMC_BASE		0x12250000
+#define EXYNOS5_UART_BASE		0x12C00000
+#define EXYNOS5_PWMTIMER_BASE		0x12DD0000
+#define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
+#define EXYNOS5_PHY0_CTRL_BASE		0x10C00000
+#define EXYNOS5_PHY1_CTRL_BASE		0x10C10000
+#endif	/* _EXYNOS5_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 9863a12..33f3273 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -20,7 +20,6 @@ 
 
 #ifndef __ASM_ARCH_GPIO_H
 #define __ASM_ARCH_GPIO_H
-
 #ifndef __ASSEMBLY__
 struct s5p_gpio_bank {
 	unsigned int	con;
@@ -75,6 +74,29 @@  struct exynos4_gpio_part2 {
 	struct s5p_gpio_bank x3;
 };
 
+struct exynos5_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank a2;
+	struct s5p_gpio_bank b0;
+	struct s5p_gpio_bank b1;
+	struct s5p_gpio_bank b2;
+	struct s5p_gpio_bank b3;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank c2;
+	struct s5p_gpio_bank c3;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+};
+
 struct exynos4_gpio_part3 {
 	struct s5p_gpio_bank z;
 };
@@ -91,7 +113,7 @@  void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 
 /* GPIO pins per bank  */
 #define GPIO_PER_BANK 8
-
+#ifdef CONFIG_EXYNOS4
 #define exynos4_gpio_part1_get_nr(bank, pin) \
 	((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
 			       EXYNOS4_GPIO_PART1_BASE)->bank)) \
@@ -107,13 +129,32 @@  void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 	    - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
 	  * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
 
+#elif defined CONFIG_EXYNOS5
+
+#define exynos5_gpio_part1_get_nr(bank, pin) \
+	((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
+			       EXYNOS5_GPIO_PART1_BASE)->bank)) \
+	    - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+	  * GPIO_PER_BANK) + pin)
+
+#define GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
+			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+#endif
+
+#ifdef CONFIG_EXYNOS4
+#define EXYNOS_GPIO_PART1_BASE	EXYNOS4_GPIO_PART1_BASE
+#define EXYNOS_GPIO_PART2_BASE	EXYNOS4_GPIO_PART2_BASE
+#elif defined CONFIG_EXYNOS5
+#define EXYNOS_GPIO_PART1_BASE	EXYNOS5_GPIO_PART1_BASE
+#endif
 static inline unsigned int s5p_gpio_base(int nr)
 {
 	if (nr < GPIO_PART1_MAX)
-		return EXYNOS4_GPIO_PART1_BASE;
+		return EXYNOS_GPIO_PART1_BASE;
+#ifdef CONFIG_EXYNOS4
 	else
-		return EXYNOS4_GPIO_PART2_BASE;
-
+		return EXYNOS_GPIO_PART2_BASE;
+#endif
 	return 0;
 }
 
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
new file mode 100644
index 0000000..a26f896
--- /dev/null
+++ b/board/samsung/smdk5250/Makefile
@@ -0,0 +1,48 @@ 
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= lowlevel_init.o
+SOBJS	+= mem_setup.o
+COBJS	+= smdk5250.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL	:=	 $(obj).depend $(LIB)
+
+all:	$(ALL)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
new file mode 100644
index 0000000..6b47826
--- /dev/null
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -0,0 +1,524 @@ 
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include "smdk5250_setup.h"
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ */
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+
+	/* use iROM stack in bl2 */
+	ldr	sp, =0x02050000
+
+	push {lr}
+
+	/* r5 has always zero */
+	mov	r5, #0
+	ldr	r7, =EXYNOS5_GPIO_PART1_BASE
+
+	/* check reset status */
+	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
+	ldr	r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* LPA wakeup reset */
+	ldr	r2, =S5P_CHECK_LPA
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in ram, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp	r1, r2			/* compare r1, r2 */
+	beq	1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl system_clock_init
+
+	/* Memory initialize */
+	bl mem_ctrl_asm_init
+
+1:
+	/* for UART */
+	bl uart_asm_init
+	bl tzpc_init
+	pop	{pc}
+
+wakeup_reset:
+	bl system_clock_init
+	bl mem_ctrl_asm_init
+	bl tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
+
+	/* r1 = physical address of exynos5_cpu_resume function*/
+	ldr	r1, [r0]
+
+	/* Jump to kernel */
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	push	{lr}
+	ldr	r0, =EXYNOS5_CLOCK_BASE
+
+	/*
+	 * MUX_APLL_SEL[0]: FINPLL = 0
+	 * MUX_CPU_SEL[6]: MOUTAPLL = 0
+	 * MUX_HPM_SEL[20]: MOUTAPLL = 0
+	 */
+	ldr	r1, =0x0
+	ldr	r2, =CLK_SRC_CPU_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_MPLL_SEL[8]: FINPLL = 0 */
+	ldr	r1, =0x0
+	ldr	r2, =CLK_SRC_CORE1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLLSRC_SEL[0]: FINPLL = 0
+	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
+	 */
+	ldr	r1, =0x0
+	ldr	r2, =CLK_SRC_TOP2_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_BPLL_SEL[0]: FINPLL = 0*/
+	ldr	r1, =0x0
+	ldr	r2, =CLK_SRC_CDREX_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_ACLK_* Clock Selection */
+	ldr	r1, =CLK_SRC_TOP0_VAL
+	ldr	r2, =CLK_SRC_TOP0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_ACLK_* Clock Selection */
+	ldr	r1, =CLK_SRC_TOP1_VAL
+	ldr	r2, =CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+
+	/* MUX_ACLK_* Clock Selection */
+	ldr	r1, =CLK_SRC_TOP3_VAL
+	ldr	r2, =CLK_SRC_TOP3_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_PWI_SEL[16:19]: SCLKMPLL = 6 */
+	ldr	r1, =CLK_SRC_CORE0_VAL
+	ldr	r2, =CLK_SRC_CORE0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_ATCLK_LEX[0]: ACLK_200 = 0*/
+	ldr	r1, =CLK_SRC_LEX_VAL
+	ldr	r2, =CLK_SRC_LEX_OFFSET
+	str	r1, [r0, r2]
+
+
+	/* UART [0:5]: SCLKMPLL = 6 */
+	ldr	r1, =CLK_SRC_PERIC0_VAL
+	ldr	r2, =CLK_SRC_PERIC0_OFFSET
+	str	r1, [r0, r2]
+
+	/* Set Clock Ratios */
+	ldr	r1, =CLK_DIV_CPU0_VAL
+	ldr	r2, =CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+
+	/* Set COPY and HPM Ratio */
+	ldr	r1, =CLK_DIV_CPU1_VAL
+	ldr	r2, =CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	/* CORED_RATIO, COREP_RATIO */
+	ldr	r1, =CLK_DIV_CORE0_VAL
+	ldr	r2, =CLK_DIV_CORE0_OFFSET
+	str	r1, [r0, r2]
+
+	/* PWI_RATIO[8:11], DVSEM_RATIO[16:22], DPM_RATIO[24:20] */
+	ldr	r1, =CLK_DIV_CORE1_VAL
+	ldr	r2, =CLK_DIV_CORE1_OFFSET
+	str	r1, [r0, r2]
+
+	/* ACLK_*_RATIO */
+	ldr	r1, =CLK_DIV_TOP0_VAL
+	ldr	r2, =CLK_DIV_TOP0_OFFSET
+	str	r1, [r0, r2]
+
+	/* ACLK_*_RATIO */
+	ldr	r1, =CLK_DIV_TOP1_VAL
+	ldr	r2, =CLK_DIV_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* CDREX Ratio */
+	ldr	r1, =CLK_DIV_CDREX_VAL
+	ldr	r2, =CLK_DIV_CDREX_OFFSET
+	str	r1, [r0, r2]
+
+	/* MCLK_EFPHY_RATIO[0:3] */
+	ldr	r1, =CLK_DIV_CDREX2_VAL
+	ldr	r2, =CLK_DIV_CDREX2_OFFSET
+	str	r1, [r0, r2]
+
+	/* {PCLK[4:6]|ATCLK[8:10]}_RATIO */
+	ldr	r1, =CLK_DIV_LEX_VAL
+	ldr	r2, =CLK_DIV_LEX_OFFSET
+	str	r1, [r0, r2]
+
+	/* PCLK_R0X_RATIO[0:3] */
+	ldr	r1, =CLK_DIV_R0X_VAL
+	ldr	r2, =CLK_DIV_R0X_OFFSET
+	str	r1, [r0, r2]
+
+	/* PCLK_R1X_RATIO[0:3] */
+	ldr	r1, =CLK_DIV_R1X_VAL
+	ldr	r2, =CLK_DIV_R1X_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
+	ldr	r1, =CLK_SRC_FSYS_VAL
+	ldr	r2, =CLK_SRC_FSYS_OFFSET
+	str	r1, [r0, r2]
+
+	/* UART[0-4] */
+	ldr	r1, =CLK_DIV_PERIC0_VAL
+	ldr	r2, =CLK_DIV_PERIC0_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA_RATIO, USB_DRD_RATIO */
+	ldr	r1, =CLK_DIV_FSYS0_VAL
+	ldr	r2, =CLK_DIV_FSYS0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[0-1] */
+	ldr	r1, =CLK_DIV_FSYS1_VAL
+	ldr	r2, =CLK_DIV_FSYS1_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[2-3] */
+	ldr	r1, =CLK_DIV_FSYS2_VAL
+	ldr	r2, =CLK_DIV_FSYS2_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[4] */
+	ldr	r1, =CLK_DIV_FSYS3_VAL
+	ldr	r2, =CLK_DIV_FSYS3_OFFSET
+	str	r1, [r0, r2]
+
+	/* ACLK|PLCK_ACP_RATIO */
+	ldr	r1, =CLK_DIV_ACP_VAL
+	ldr	r2, =CLK_DIV_ACP_OFFSET
+	str	r1, [r0, r2]
+
+	/* ISPDIV0_RATIO, ISPDIV1_RATIO */
+	ldr	r1, =CLK_DIV_ISP0_VAL
+	ldr	r2, =CLK_DIV_ISP0_OFFSET
+	str	r1, [r0, r2]
+
+	/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
+	ldr	r1, =CLK_DIV_ISP1_VAL
+	ldr	r2, =CLK_DIV_ISP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* MPWMDIV_RATIO */
+	ldr	r1, =CLK_DIV_ISP2_VAL
+	ldr	r2, =CLK_DIV_ISP2_OFFSET
+	str	r1, [r0, r2]
+
+	/* PLL locktime */
+	ldr	r1, =APLL_LOCK_VAL
+	ldr	r2, =APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =MPLL_LOCK_VAL
+	ldr	r2, =MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =BPLL_LOCK_VAL
+	ldr	r2, =BPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =CPLL_LOCK_VAL
+	ldr	r2, =CPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =EPLL_LOCK_VAL
+	ldr	r2, =EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	ldr	r1, =VPLL_LOCK_VAL
+	ldr	r2, =VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #0x10000
+2:	subs	r1, r1, #1
+	bne	2b
+
+
+	/* Set APLL */
+	ldr	r1, =APLL_CON1_VAL
+	ldr	r2, =APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =APLL_CON0_VAL
+	ldr	r2, =APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	mov	r1, #0x30000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	/* Set MPLL */
+	ldr	r1, =MPLL_CON1_VAL
+	ldr	r2, =MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =MPLL_CON0_VAL
+	ldr	r2, =MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+4:	subs	r1, r1, #1
+	bne	4b
+
+	/* Set BPLL */
+	ldr	r1, =BPLL_CON1_VAL
+	ldr	r2, =BPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =BPLL_CON0_VAL
+	ldr	r2, =BPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+5:	subs	r1, r1, #1
+	bne	5b
+
+	/* Set CPLL */
+	ldr	r1, =CPLL_CON1_VAL
+	ldr	r2, =CPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =CPLL_CON0_VAL
+	ldr	r2, =CPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+6:	subs	r1, r1, #1
+	bne	6b
+
+	/* Set EPLL */
+	ldr	r1, =EPLL_CON2_VAL
+	ldr	r2, =EPLL_CON2_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =EPLL_CON1_VAL
+	ldr	r2, =EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =EPLL_CON0_VAL
+	ldr	r2, =EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+7:	subs	r1, r1, #1
+	bne	7b
+
+	/* Set VPLL */
+	ldr	r1, =VPLL_CON2_VAL
+	ldr	r2, =VPLL_CON2_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =VPLL_CON1_VAL
+	ldr	r2, =VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =VPLL_CON0_VAL
+	ldr	r2, =VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+8:	subs	r1, r1, #1
+	bne	8b
+
+	/* After Initiallising th PLL select the sources accordingly */
+	/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
+	ldr	r1, =CLK_SRC_CPU_VAL
+	ldr	r2, =CLK_SRC_CPU_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
+	ldr	r1, =CLK_SRC_CORE1_VAL
+	ldr	r2, =CLK_SRC_CORE1_OFFSET
+	str	r1, [r0, r2]
+
+	/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
+	ldr	r1, =CLK_SRC_CDREX_VAL
+	ldr	r2, =CLK_SRC_CDREX_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLLSRC_SEL[0]: FINPLL = 0
+	 * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
+	 * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
+	 */
+	ldr	r1, =CLK_SRC_TOP2_VAL
+	ldr	r2, =CLK_SRC_TOP2_OFFSET
+	str	r1, [r0, r2]
+
+	pop	{pc}
+
+
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+	.globl uart_asm_init
+uart_asm_init:
+
+	/* setup UART0-UART3 GPIOs (part1) */
+	mov	r0, r7
+	ldr	r1, =EXYNOS5_GPIO_A0_CON_VAL
+	str	r1, [r0, #EXYNOS5_GPIO_A0_CON_OFFSET]
+	ldr	r1, =EXYNOS5_GPIO_A1_CON_VAL
+	str	r1, [r0, #EXYNOS5_GPIO_A1_CON_OFFSET]
+
+	ldr r0, =EXYNOS5_UART_BASE
+	add r0, r0, #EXYNOS5_DEFAULT_UART_OFFSET
+
+	ldr	r1, =ULCON_VAL
+	str	r1, [r0, #ULCON_OFFSET]
+	ldr	r1, =UCON_VAL
+	str	r1, [r0, #UCON_OFFSET]
+	ldr	r1, =UFCON_VAL
+	str	r1, [r0, #UFCON_OFFSET]
+	ldr	r1, =UBRDIV_VAL
+	str	r1, [r0, #UBRDIV_OFFSET]
+	ldr	r1, =UFRACVAL_VAL
+	str	r1, [r0, #UFRACVAL_OFFSET]
+	ldr	r1, =0x4f
+	str	r1, [r0, #UTXH_OFFSET]		@'O'
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/* Setting TZPC[TrustZone Protection Controller] */
+tzpc_init:
+
+	ldr	r0, =TZPC0_BASE
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC1_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC2_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC3_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC4_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC5_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC6_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC7_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC8_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
+
+	ldr	r0, =TZPC9_BASE
+	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
+	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
+
+	mov	pc, lr
+
diff --git a/board/samsung/smdk5250/mem_setup.S b/board/samsung/smdk5250/mem_setup.S
new file mode 100644
index 0000000..a7cc54b
--- /dev/null
+++ b/board/samsung/smdk5250/mem_setup.S
@@ -0,0 +1,600 @@ 
+/*
+ * Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <config.h>
+#include "smdk5250_setup.h"
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_533*/
+/* LPDDR support: LPDDR2 */
+
+/* (Memory Interleaving Size = 1 << IV_SIZE) */
+#define CONFIG_IV_SIZE 0x07
+#define RD_LVL		1
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	push	{lr}
+
+	/* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
+	ldr	r0, =EXYNOS5_CLOCK_BASE
+
+	/* Reset PHY Controllor */
+	ldr	r1, =0x0
+	ldr	r2, =LPDDR3PHY_CTRL
+	str	r1, [r0, r2]
+
+	bl	delay
+
+	/*set Read Latance and Burst Length for PHY0 and PHY1 */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x408
+	str	r1, [r0, #DMC_PHY_CON42]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x408
+	str	r1, [r0, #DMC_PHY_CON42]
+
+	/*
+	 * ZQ Calibration:
+	 * Select Driver Strength,
+	 * long calibration for manual calibration
+	 */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x0DA40304
+	str	r1, [r0, #DMC_PHY_CON16]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x0DA40304
+	str	r1, [r0, #DMC_PHY_CON16]
+
+	/* Enable termination */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x0DAC0304
+	str	r1, [r0, #DMC_PHY_CON16]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x0DAC0304
+	str	r1, [r0, #DMC_PHY_CON16]
+
+	/* Start Manual Calibration */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x0DAC0306
+	str	r1, [r0, #DMC_PHY_CON16]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x0DAC0306
+	str	r1, [r0, #DMC_PHY_CON16]
+
+	bl	delay
+
+	/* Enable termination */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x0DAC0304
+	str	r1, [r0, #DMC_PHY_CON16]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x0DAC0304
+	str	r1, [r0, #DMC_PHY_CON16]
+
+	/* DDR Mode: LPDDR2 */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x17021240
+	str	r1, [r0, #DMC_PHY_CON0]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x17021240
+	str	r1, [r0, #DMC_PHY_CON0]
+
+	/* DQS, DQ: Signal, for LPDDR2: Always Set */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x00000F0F
+	str	r1, [r0, #DMC_PHY_CON14]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x00000F0F
+	str	r1, [r0, #DMC_PHY_CON14]
+
+	/* RD_FETCH: 1 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x1FFF1000
+	str	r1, [r0, #DMC_CONCONTROL]
+	bl	delay
+
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x0FFF1000
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	bl	delay
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Reset Force DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/*
+	 * Dynamic Clock: Always Running
+	 * Memory Burst length: 4
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: LPDDR2-S4
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	ldr	r1, =0x00212500
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	/*
+	 * Memory Configuration Chip 0
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x00001323
+	str	r1, [r0, #DMC_MEMCONFIG0]
+
+	/*
+	 * Memory Configuration Chip 1
+	 * Address Mapping: Interleaved
+	 * Number of Column address Bits: 10 bits
+	 * Number of Rows Address Bits: 14
+	 * Number of Banks: 8
+	 */
+	ldr	r1, =0x00001323
+	str	r1, [r0, #DMC_MEMCONFIG1]
+
+	/*
+	 * Chip0: AXI
+	 * AXI Base Address: 0x40000000
+	 * AXI Base Address Mask: 0x780
+	 */
+	ldr	r1, =0x00400780
+	str	r1, [r0, #DMC_MEMBASECONFIG0]
+
+	/*
+	 * Chip1: AXI
+	 * AXI Base Address: 0x80000000
+	 * AXI Base Address Mask: 0x780
+	 */
+	ldr	r1, =0x00800780
+	str	r1, [r0, #DMC_MEMBASECONFIG1]
+
+	/* Precharge Configuration */
+	ldr	r1, =0xFF000000
+	str	r1, [r0, #DMC_PRECHCONFIG]
+
+	/* Power Down mode Configuration */
+	ldr	r1, =0xFFFF00FF
+	str	r1, [r0, #DMC_PWRDNCONFIG]
+
+	/* Periodic Refrese Interval */
+	ldr	r1, =0x0000005D
+	str	r1, [r0, #DMC_TIMINGAREF]
+
+	/* MCLK_CDREX_533 */
+	/*
+	 * TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	ldr	r1, =0x2336544C
+	str	r1, [r0, #DMC_TIMINGROW]
+
+	ldr	r1, =0x24202408
+	str	r1, [r0, #DMC_TIMINGDATA]
+
+	ldr	r1, =0x38260235
+	str	r1, [r0, #DMC_TIMINGPOWER]
+
+	/* Memory Channel Inteleaving Size: 128 Bytes */
+	ldr	r1, =CONFIG_IV_SIZE
+	str	r1, [r0, #DMC_IVCONTROL]
+
+	/* Set Offsets to read DQS */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x7F7F7F7F
+	str	r1, [r0, #DMC_PHY_CON4]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x7F7F7F7F
+	str	r1, [r0, #DMC_PHY_CON4]
+
+	/* Set Offsets to read DQ */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x7F7F7F7F
+	str	r1, [r0, #DMC_PHY_CON6]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x7F7F7F7F
+	str	r1, [r0, #DMC_PHY_CON6]
+
+	/* Debug Offset */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x0000007F
+	str	r1, [r0, #DMC_PHY_CON10]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x0000007F
+	str	r1, [r0, #DMC_PHY_CON10]
+
+	/* Start DLL Locking */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x10107F50
+	str	r1, [r0, #DMC_PHY_CON12]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x10107F50
+	str	r1, [r0, #DMC_PHY_CON12]
+
+	bl	delay
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Reset DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/*
+	 * NOP CMD: Channel 0, Chip 0
+	 * Exit from active/precharge power down or deep power down
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x07000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00071C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x00010BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* MCLK_CDREX_533 */
+	ldr	r1, =0x00000708
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x00000818
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/*
+	 * NOP CMD: Channel 0, Chip 1
+	 * Exit from active/precharge power down or deep power down
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x07100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x00171C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x00110BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* MCLK_CDREX_533 */
+	ldr	r1, =0x00100708
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x00100818
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/*
+	 * NOP CMD: Channel 1, Chip 0
+	 * Exit from active/precharge power down or deep power down
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x17000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x10071C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x10010BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* MCLK_CDREX_533 */
+	ldr	r1, =0x10000708
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x10000818
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/*
+	 * NOP CMD: Channel 1, Chip 1
+	 * Exit from active/precharge power down or deep power down
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x17100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	ldr	r1, =0x10171C00
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x10110BFC
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* MCLK_CDREX_533 */
+	ldr	r1, =0x10100708
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	ldr	r1, =0x10100818
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* Reset DQS Offsets */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x08080808
+	str	r1, [r0, #DMC_PHY_CON4]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x08080808
+	str	r1, [r0, #DMC_PHY_CON4]
+
+	/* Reset DQ Offsets */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x08080808
+	str	r1, [r0, #DMC_PHY_CON6]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x08080808
+	str	r1, [r0, #DMC_PHY_CON6]
+
+	/* Reset debug Offsets */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHY_CON10]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHY_CON10]
+
+	/* Set DLL Locking */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x10107F30
+	str	r1, [r0, #DMC_PHY_CON12]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x10107F30
+	str	r1, [r0, #DMC_PHY_CON12]
+
+	bl	delay
+
+	/* Start DLL Locking */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x10107F70
+	str	r1, [r0, #DMC_PHY_CON12]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x10107F70
+	str	r1, [r0, #DMC_PHY_CON12]
+
+	bl	delay
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Reset DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	bl	delay
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Reset DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	bl	delay
+#if defined(RD_LVL)
+	/* DLL On */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x10102D50
+	str	r1, [r0, #DMC_PHY_CON12]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x10102D50
+	str	r1, [r0, #DMC_PHY_CON12]
+
+	/*
+	 * Set ctrl_gateadj, ctrl_readadj
+	 * ctrl_gateduradj, rdlvl_pass_adj
+	 * rdlvl_rddataPadj
+	 */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x09210001
+	str	r1, [r0, #DMC_PHY_CON1]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x09210001
+	str	r1, [r0, #DMC_PHY_CON1]
+
+	/* LPDDR2 Address */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x00000208
+	str	r1, [r0, #DMC_PHY_CON22]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x00000208
+	str	r1, [r0, #DMC_PHY_CON22]
+
+	/* Enable Byte Read Leleling */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x17023240
+	str	r1, [r0, #DMC_PHY_CON0]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x17023240
+	str	r1, [r0, #DMC_PHY_CON0]
+
+	/* rdlvl_en: Use levelling offset instead ctrl_shiftc */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x02010004
+	str	r1, [r0, #DMC_PHY_CON2]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x02010004
+	str	r1, [r0, #DMC_PHY_CON2]
+
+	bl	delay
+
+	/* Enable Data Eye Trainig */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000002
+	str	r1, [r0, #DMC_RDLVL_CONFIG]
+
+	bl	delay
+
+	/* Disable Data Eye Trainig */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_RDLVL_CONFIG]
+
+	/* RdDeSkew_clear: Clear */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x02012004
+	str	r1, [r0, #DMC_PHY_CON2]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x02012004
+	str	r1, [r0, #DMC_PHY_CON2]
+
+	/* Start DLL Locking */
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x10107F70
+	str	r1, [r0, #DMC_PHY_CON12]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x10107F70
+	str	r1, [r0, #DMC_PHY_CON12]
+
+	/* Force DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000008
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	/* Reset DLL Resyncronization */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00000000
+	str	r1, [r0, #DMC_PHYCONTROL0]
+
+	bl	delay
+
+	/* ctrl_atgate: ctrl_gate_p*, ctrl_read_p* generated by PHY*/
+	ldr	r0, =EXYNOS5_PHY0_CTRL_BASE
+	ldr	r1, =0x17023200
+	str	r1, [r0, #DMC_PHY_CON0]
+	ldr	r0, =EXYNOS5_PHY1_CTRL_BASE
+	ldr	r1, =0x17023200
+	str	r1, [r0, #DMC_PHY_CON0]
+
+	/* Channel:0, Chip:0, PALL (all banks precharge) CMD */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x01000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* Channel:0, Chip:1, PALL (all banks precharge) CMD */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x01100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* Channel:1, Chip:0, PALL (all banks precharge) CMD */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x11000000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+
+	/* Channel:1, Chip:1, PALL (all banks precharge) CMD */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x11100000
+	str	r1, [r0, #DMC_DIRECTCMD]
+
+	bl	delay
+#endif
+	/*
+	 * Dynamic Clock: Stops During Idle Period
+	 * Dynamic Power Down: Enable
+	 * Dynamic Self refresh: Enable
+	 * Memory Burst length: 4
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: LPDDR2-S4
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x00212523
+	str	r1, [r0, #DMC_MEMCONTROL]
+
+	/* Start Auto refresh */
+	ldr	r0, =EXYNOS5_DMC_CTRL_BASE
+	ldr	r1, =0x0FFF10E0
+	str	r1, [r0, #DMC_CONCONTROL]
+
+	pop	{lr}
+	mov	pc, lr
+
+delay:
+	mov	r2, #0x10000
+delayloop:
+	subs	r2, r2, #1
+	bne	delayloop
+	mov	pc, lr
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
new file mode 100644
index 0000000..0ea9a32
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -0,0 +1,125 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct exynos5_gpio_part1 *gpio1;
+
+int board_init(void)
+{
+	gpio1 = (struct exynos5_gpio_part1 *) EXYNOS5_GPIO_PART1_BASE;
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+							PHYS_SDRAM_2_SIZE);
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+							PHYS_SDRAM_3_SIZE);
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+							PHYS_SDRAM_4_SIZE);
+	gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
+	gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5, \
+							PHYS_SDRAM_5_SIZE);
+	gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
+	gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6, \
+							PHYS_SDRAM_6_SIZE);
+	gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
+	gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7, \
+							PHYS_SDRAM_7_SIZE);
+	gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
+	gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8, \
+							PHYS_SDRAM_8_SIZE);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: SMDK5250\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPC2[0]	SD_2_CLK(2)
+	 * GPC2[1]	SD_2_CMD(2)
+	 * GPC2[2]	SD_2_CDn
+	 * GPC2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		/* GPC2[0:6] special function 2 */
+		s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == 0 || i == 1) {
+			s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
+	}
+
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
diff --git a/board/samsung/smdk5250/smdk5250_setup.h b/board/samsung/smdk5250/smdk5250_setup.h
new file mode 100644
index 0000000..0834725
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_setup.h
@@ -0,0 +1,583 @@ 
+/*
+ * Machine Specific Values for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* Offsets of clock registers (sources and dividers) */
+#define CLK_SRC_CPU_OFFSET	0x00200
+#define CLK_DIV_CPU0_OFFSET	0x00500
+#define CLK_DIV_CPU1_OFFSET	0x00504
+
+#define CLK_SRC_CORE0_OFFSET	0x04200
+#define CLK_DIV_CORE0_OFFSET	0x04500
+
+#define CLK_SRC_CORE1_OFFSET	0x04204
+#define CLK_DIV_CORE1_OFFSET	0x04504
+
+#define CLK_SRC_TOP0_OFFSET	0x10210
+#define CLK_SRC_TOP1_OFFSET	0x10214
+#define CLK_SRC_TOP2_OFFSET	0x10218
+#define CLK_SRC_TOP3_OFFSET	0x1021C
+#define CLK_DIV_TOP0_OFFSET	0x10510
+#define CLK_DIV_TOP1_OFFSET	0x10514
+
+#define CLK_SRC_FSYS_OFFSET	0x10244
+#define CLK_DIV_FSYS0_OFFSET	0x10548
+#define CLK_DIV_FSYS1_OFFSET	0x1054C
+#define CLK_DIV_FSYS2_OFFSET	0x10550
+#define CLK_DIV_FSYS3_OFFSET	0x10554
+
+#define CLK_SRC_PERIC0_OFFSET	0x10250
+#define CLK_DIV_PERIC0_OFFSET	0x10558
+
+#define CLK_SRC_LEX_OFFSET	0x14200
+#define CLK_DIV_LEX_OFFSET	0x14500
+
+#define CLK_DIV_R0X_OFFSET	0x18500
+#define CLK_DIV_R1X_OFFSET	0x1C500
+
+
+#define CLK_SRC_CDREX_OFFSET	0x20200
+#define CLK_DIV_CDREX_OFFSET	0x20500
+#define CLK_DIV_CDREX2_OFFSET	0x20504
+
+#define CLK_DIV_ACP_OFFSET	0x08500
+#define CLK_DIV_ISP0_OFFSET	0x0C300
+#define CLK_DIV_ISP1_OFFSET	0x0C304
+#define CLK_DIV_ISP2_OFFSET	0x0C308
+
+
+#define APLL_LOCK_OFFSET	0x00000
+#define MPLL_LOCK_OFFSET	0x04000
+#define APLL_CON0_OFFSET	0x00100
+#define APLL_CON1_OFFSET	0x00104
+#define MPLL_CON0_OFFSET	0x04100
+#define MPLL_CON1_OFFSET	0x04104
+
+#define BPLL_LOCK_OFFSET	0x20010
+#define BPLL_CON0_OFFSET	0x20110
+#define BPLL_CON1_OFFSET	0x20114
+
+#define CPLL_LOCK_OFFSET	0x10020
+#define EPLL_LOCK_OFFSET	0x10030
+#define VPLL_LOCK_OFFSET	0x10040
+
+#define CPLL_CON0_OFFSET	0x10120
+#define CPLL_CON1_OFFSET	0x10124
+
+#define EPLL_CON0_OFFSET	0x10130
+#define EPLL_CON1_OFFSET	0x10134
+#define EPLL_CON2_OFFSET	0x10138
+
+#define VPLL_CON0_OFFSET	0x10140
+#define VPLL_CON1_OFFSET	0x10144
+#define VPLL_CON2_OFFSET	0x10148
+
+
+/* DMC: DRAM Controllor Register offsets */
+#define DMC_CONCONTROL		0x00
+#define DMC_MEMCONTROL		0x04
+#define DMC_MEMCONFIG0		0x08
+#define DMC_MEMCONFIG1		0x0C
+#define DMC_DIRECTCMD		0x10
+#define DMC_PRECHCONFIG		0x14
+#define DMC_PHYCONTROL0		0x18
+#define DMC_PWRDNCONFIG		0x28
+#define DMC_TIMINGAREF		0x30
+#define DMC_TIMINGROW		0x34
+#define DMC_TIMINGDATA		0x38
+#define DMC_TIMINGPOWER		0x3C
+#define DMC_IVCONTROL		0xF0
+#define DMC_RDLVL_CONFIG	0xF8
+#define DMC_MEMBASECONFIG0	0x010C
+#define DMC_MEMBASECONFIG1	0x0110
+#define LPDDR3PHY_CTRL		0x20A10
+
+#define DMC_PHY_CON0		0x00
+#define DMC_PHY_CON1		0x04
+#define DMC_PHY_CON10		0x28
+#define DMC_PHY_CON12		0x30
+#define DMC_PHY_CON14		0x38
+#define DMC_PHY_CON16		0x40
+#define DMC_PHY_CON2		0x08
+#define DMC_PHY_CON22		0x5C
+#define DMC_PHY_CON4		0x10
+#define DMC_PHY_CON42		0xAC
+#define DMC_PHY_CON6		0x18
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET		0x800
+#define INFORM1_OFFSET		0x804
+
+/* GPIO Offsets for UART: GPIO Contol Register */
+#define EXYNOS5_GPIO_A0_CON_OFFSET	0x0
+#define EXYNOS5_GPIO_A1_CON_OFFSET	0x20
+
+/* UART Register offsets */
+#define ULCON_OFFSET		0x00
+#define UCON_OFFSET		0x04
+#define UFCON_OFFSET		0x08
+#define UBRDIV_OFFSET		0x28
+#define UFRACVAL_OFFSET		0x2C
+#define UTXH_OFFSET		0x20
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE		0x10100000
+#define TZPC1_BASE		0x10110000
+#define TZPC2_BASE		0x10120000
+#define TZPC3_BASE		0x10130000
+#define TZPC4_BASE		0x10140000
+#define TZPC5_BASE		0x10150000
+#define TZPC6_BASE		0x10160000
+#define TZPC7_BASE		0x10170000
+#define TZPC8_BASE		0x10180000
+#define TZPC9_BASE		0x10190000
+
+#define TZPC_DECPROT0SET_OFFSET	0x804
+#define TZPC_DECPROT1SET_OFFSET	0x810
+#define TZPC_DECPROT2SET_OFFSET	0x81C
+#define TZPC_DECPROT3SET_OFFSET	0x828
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL	*/
+#define MUX_HPM_SEL		0
+#define MUX_CPU_SEL		0
+#define MUX_APLL_SEL		1
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20) \
+				| (MUX_CPU_SEL << 16) \
+				| (MUX_APLL_SEL))
+
+/* CLK_DIV_CPU0	*/
+#define ARM2_RATIO		0x0
+#define APLL_RATIO		0x1
+#define PCLK_DBG_RATIO		0x1
+#define ATB_RATIO		0x4
+#define PERIPH_RATIO		0x7
+#define ACP_RATIO		0x7
+#define CPUD_RATIO		0x2
+#define ARM_RATIO		0x0
+#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28) \
+				| (APLL_RATIO << 24) \
+				| (PCLK_DBG_RATIO << 20) \
+				| (ATB_RATIO << 16) \
+				| (PERIPH_RATIO << 12) \
+				| (ACP_RATIO << 8) \
+				| (CPUD_RATIO << 4) \
+				| (ARM_RATIO))
+
+/* CLK_DIV_CPU1	*/
+#define HPM_RATIO		0x4
+#define COPY_RATIO		0x0
+#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) \
+				| (COPY_RATIO))
+
+#define APLL_MDIV		0x7D
+#define APLL_PDIV		0x3
+#define APLL_SDIV		0x0
+
+#define MPLL_MDIV		0x64
+#define MPLL_PDIV		0x3
+#define MPLL_SDIV		0x0
+
+#define CPLL_MDIV		0x96
+#define CPLL_PDIV		0x4
+#define CPLL_SDIV		0x0
+
+/* APLL_CON1	*/
+#define APLL_CON1_VAL	(0x00203800)
+
+/* MPLL_CON1	*/
+#define MPLL_CON1_VAL	(0x00203800)
+
+/* CPLL_CON1	*/
+#define CPLL_CON1_VAL	(0x00203800)
+
+#define EPLL_MDIV	0x60
+#define EPLL_PDIV	0x3
+#define EPLL_SDIV	0x3
+
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
+
+#define VPLL_MDIV	0x96
+#define VPLL_PDIV	0x3
+#define VPLL_SDIV	0x2
+
+#define VPLL_CON1_VAL	0x00000000
+#define VPLL_CON2_VAL	0x00000080
+
+#define BPLL_MDIV	0x215
+#define BPLL_PDIV	0xC
+#define BPLL_SDIV	0x1
+
+#define BPLL_CON1_VAL	0x00203800
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+#define APLL_CON0_VAL	set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+#define MPLL_CON0_VAL	set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+#define CPLL_CON0_VAL	set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
+#define EPLL_CON0_VAL	set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+#define VPLL_CON0_VAL	set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+#define BPLL_CON0_VAL	set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL	0x00060000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL	0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL	0x120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL	0x07070700
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL	0x111
+
+/* CLK_DIV_CDREX */
+#define MCLK_CDREX2_RATIO	0x0
+#define ACLK_EFCON_RATIO	0x1
+#define MCLK_DPHY_RATIO		0x0
+#define MCLK_CDREX_RATIO	0x0
+#define ACLK_C2C_200_RATIO	0x1
+#define C2C_CLK_400_RATIO	0x1
+#define PCLK_CDREX_RATIO	0x3
+#define ACLK_CDREX_RATIO	0x1
+#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 20) \
+				| (MCLK_CDREX_RATIO << 16) \
+				| (ACLK_C2C_200_RATIO << 12) \
+				| (C2C_CLK_400_RATIO << 8) \
+				| (PCLK_CDREX_RATIO << 4) \
+				| (ACLK_CDREX_RATIO))
+
+#define MCLK_EFPHY_RATIO	0x4
+#define CLK_DIV_CDREX2_VAL	MCLK_EFPHY_RATIO
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL	0x12
+
+/* CLK_SRC_TOP0	*/
+#define MUX_ACLK_300_GSCL_SEL		0x1
+#define MUX_ACLK_300_GSCL_MID_SEL	0x0
+#define MUX_ACLK_400_SEL		0x0
+#define MUX_ACLK_333_SEL		0x0
+#define MUX_ACLK_300_DISP1_SEL		0x1
+#define MUX_ACLK_300_DISP1_MID_SEL	0x0
+#define MUX_ACLK_200_SEL		0x0
+#define MUX_ACLK_166_SEL		0x0
+#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL << 25) \
+				| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+				| (MUX_ACLK_400_SEL << 20) \
+				| (MUX_ACLK_333_SEL << 16) \
+				| (MUX_ACLK_300_DISP1_SEL << 15) \
+				| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
+				| (MUX_ACLK_200_SEL << 12) \
+				| (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1	*/
+#define MUX_ACLK_400_ISP_SEL		0x0
+#define MUX_ACLK_400_IOP_SEL		0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL	0x0
+#define CLK_SRC_TOP1_VAL		((MUX_ACLK_400_ISP_SEL << 24) \
+					|(MUX_ACLK_400_IOP_SEL << 20) \
+					|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+
+/* CLK_SRC_TOP2 */
+#define MUX_BPLL_USER_SEL	0x1
+#define MUX_MPLL_USER_SEL	0x1
+#define MUX_VPLL_SEL		0x0
+#define MUX_EPLL_SEL		0x0
+#define MUX_CPLL_SEL		0x0
+#define VPLLSRC_SEL		0x0
+#define CLK_SRC_TOP2_VAL	((MUX_BPLL_USER_SEL << 24) \
+				| (MUX_MPLL_USER_SEL << 20) \
+				| (MUX_VPLL_SEL << 16) \
+				| (MUX_EPLL_SEL << 12) \
+				| (MUX_CPLL_SEL << 8) \
+				| (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL		0x1
+#define MUX_ACLK_400_SUB_SEL		0x1
+#define MUX_ACLK_266_ISP_SUB_SEL	0x1
+#define MUX_ACLK_266_GPS_SUB_SEL	0x1
+#define MUX_ACLK_300_GSCL_SUB_SEL	0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL	0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL	0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL	0x1
+#define CLK_SRC_TOP3_VAL		((MUX_ACLK_333_SUB_SEL << 24) \
+					| (MUX_ACLK_400_SUB_SEL << 20) \
+					| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+					| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+					| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+					| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+					| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+					| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0	*/
+#define ACLK_300_RATIO		0x0
+#define ACLK_400_RATIO		0x3
+#define ACLK_333_RATIO		0x2
+#define ACLK_266_RATIO		0x2
+#define ACLK_200_RATIO		0x3
+#define ACLK_166_RATIO		0x5
+#define ACLK_133_RATIO		0x1
+#define ACLK_66_RATIO		0x5
+#define CLK_DIV_TOP0_VAL	((ACLK_300_RATIO << 28) \
+				| (ACLK_400_RATIO << 24) \
+				| (ACLK_333_RATIO << 20) \
+				| (ACLK_266_RATIO << 16) \
+				| (ACLK_200_RATIO << 12) \
+				| (ACLK_166_RATIO << 8) \
+				| (ACLK_133_RATIO << 4) \
+				| (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1	*/
+#define ACLK_MIPI_HSI_TX_BASE_RATIO	0x3
+#define ACLK_66_PRE_RATIO	0x1
+#define ACLK_400_ISP_RATIO	0x1
+#define ACLK_400_IOP_RATIO	0x1
+#define ACLK_300_GSCL_RATIO	0x0
+#define ACLK_266_GPS_RATIO	0x7
+
+#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+				| (ACLK_66_PRE_RATIO << 24) \
+				| (ACLK_400_ISP_RATIO << 20) \
+				| (ACLK_400_IOP_RATIO << 16) \
+				| (ACLK_300_GSCL_RATIO << 12) \
+				| (ACLK_266_GPS_RATIO << 8))
+
+/* APLL_LOCK	*/
+#define APLL_LOCK_VAL		(0x3E8)
+/* MPLL_LOCK	*/
+#define MPLL_LOCK_VAL		(0x2F1)
+/* CPLL_LOCK	*/
+#define CPLL_LOCK_VAL		(0x3E8)
+/* EPLL_LOCK	*/
+#define EPLL_LOCK_VAL		(0x2321)
+/* VPLL_LOCK	*/
+#define VPLL_LOCK_VAL		(0x2321)
+/* BPLL_LOCK	*/
+#define BPLL_LOCK_VAL		(0x3E8)
+
+/* CLK_SRC_PERIC0 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define PWM_SEL			0
+#define UART4_SEL		6
+#define UART3_SEL		6
+#define UART2_SEL		6
+#define UART1_SEL		6
+#define UART0_SEL		6
+#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24) \
+				| (UART4_SEL << 16) \
+				| (UART3_SEL << 12) \
+				| (UART2_SEL << 8) \
+				| (UART1_SEL << 4) \
+				| (UART0_SEL << 0))
+
+#define CLK_SRC_FSYS_VAL	0x66666
+#define CLK_DIV_FSYS0_VAL	0x0BB00000
+#define CLK_DIV_FSYS1_VAL	0x000f000f
+#define CLK_DIV_FSYS2_VAL	0x020f020f
+#define CLK_DIV_FSYS3_VAL	0x000f
+
+/* CLK_DIV_PERIC0	*/
+#define UART5_RATIO		8
+#define UART4_RATIO		8
+#define UART3_RATIO		8
+#define UART2_RATIO		8
+#define UART1_RATIO		8
+#define UART0_RATIO		8
+#define CLK_DIV_PERIC0_VAL	((UART4_RATIO << 16) \
+				| (UART3_RATIO << 12) \
+				| (UART2_RATIO << 8) \
+				| (UART1_RATIO << 4) \
+				| (UART0_RATIO << 0))
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL		0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL		0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL		0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL		0x10
+
+/* SCLK_SRC_ISP */
+#define SCLK_SRC_ISP_VAL	0x600
+/* CLK_DIV_ISP0 */
+#define CLK_DIV_ISP0_VAL	0x31
+
+/* CLK_DIV_ISP1 */
+#define CLK_DIV_ISP1_VAL	0x0
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL	0x1
+
+#define MPLL_DEC	(MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+
+#define DISABLE			0
+#define ENABLE			1
+
+/*
+ * UART GPIO_A0/GPIO_A1 Control Register Value
+ * 0x2: UART Function
+ */
+#define EXYNOS5_GPIO_A0_CON_VAL	0x22222222
+#define EXYNOS5_GPIO_A1_CON_VAL	0x222222
+
+/* ULCON: UART Line Control Value 8N1 */
+#define WORD_LEN_5_BIT		0x00
+#define WORD_LEN_6_BIT		0x01
+#define WORD_LEN_7_BIT		0x02
+#define WORD_LEN_8_BIT		0x03
+
+#define STOP_BIT_1		0x00
+#define STOP_BIT_2		0x01
+
+#define NO_PARITY			0x00
+#define ODD_PARITY			0x4
+#define EVEN_PARITY			0x5
+#define FORCED_PARITY_CHECK_AS_1	0x6
+#define FORCED_PARITY_CHECK_AS_0	0x7
+
+#define INFRAMODE_NORMAL		0x00
+#define INFRAMODE_INFRARED		0x01
+
+#define ULCON_VAL		((INFRAMODE_NORMAL << 6) \
+				| (NO_PARITY << 3) \
+				| (STOP_BIT_1 << 2) \
+				| (WORD_LEN_8_BIT << 0))
+
+/*
+ * UCON: UART Control Value
+ * Tx_interrupt Type: Level
+ * Rx_interrupt Type: Level
+ * Rx Timeout Enabled: Yes
+ * Rx-Error Atatus_Int Enable: Yes
+ * Loop_Back: No
+ * Break Signal: No
+ * Transmit mode : Interrupt request/polling
+ * Receive mode : Interrupt request/polling
+ */
+#define TX_PULSE_INTERRUPT	0
+#define TX_LEVEL_INTERRUPT	1
+#define RX_PULSE_INTERRUPT	0
+#define RX_LEVEL_INTERRUPT	1
+
+#define RX_TIME_OUT		ENABLE
+#define RX_ERROR_STATE_INT_ENB	ENABLE
+#define LOOP_BACK		DISABLE
+#define BREAK_SIGNAL		DISABLE
+
+#define TX_MODE_DISABLED	0X00
+#define TX_MODE_IRQ_OR_POLL	0X01
+#define TX_MODE_DMA		0X02
+
+#define RX_MODE_DISABLED	0X00
+#define RX_MODE_IRQ_OR_POLL	0X01
+#define RX_MODE_DMA		0X02
+
+#define UCON_VAL		((TX_LEVEL_INTERRUPT << 9) \
+				| (RX_LEVEL_INTERRUPT << 8) \
+				| (RX_TIME_OUT << 7) \
+				| (RX_ERROR_STATE_INT_ENB << 6) \
+				| (LOOP_BACK << 5) \
+				| (BREAK_SIGNAL << 4) \
+				| (TX_MODE_IRQ_OR_POLL << 2) \
+				| (RX_MODE_IRQ_OR_POLL << 0))
+
+/*
+ * UFCON: UART FIFO Control Value
+ * Tx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Rx FIFO Trigger LEVEL: 2 Bytes (001)
+ * Tx Fifo Reset: No
+ * Rx Fifo Reset: No
+ * FIFO Enable: Yes
+ */
+#define TX_FIFO_TRIGGER_LEVEL_0_BYTES	0x00
+#define TX_FIFO_TRIGGER_LEVEL_2_BYTES	0x1
+#define TX_FIFO_TRIGGER_LEVEL_4_BYTES	0x2
+#define TX_FIFO_TRIGGER_LEVEL_6_BYTES	0x3
+#define TX_FIFO_TRIGGER_LEVEL_8_BYTES	0x4
+#define TX_FIFO_TRIGGER_LEVEL_10_BYTES	0x5
+#define TX_FIFO_TRIGGER_LEVEL_12_BYTES	0x6
+#define TX_FIFO_TRIGGER_LEVEL_14_BYTES	0x7
+
+#define RX_FIFO_TRIGGER_LEVEL_2_BYTES	0x0
+#define RX_FIFO_TRIGGER_LEVEL_4_BYTES	0x1
+#define RX_FIFO_TRIGGER_LEVEL_6_BYTES	0x2
+#define RX_FIFO_TRIGGER_LEVEL_8_BYTES	0x3
+#define RX_FIFO_TRIGGER_LEVEL_10_BYTES	0x4
+#define RX_FIFO_TRIGGER_LEVEL_12_BYTES	0x5
+#define RX_FIFO_TRIGGER_LEVEL_14_BYTES	0x6
+#define RX_FIFO_TRIGGER_LEVEL_16_BYTES	0x7
+
+#define TX_FIFO_TRIGGER_LEVEL		TX_FIFO_TRIGGER_LEVEL_2_BYTES
+#define RX_FIFO_TRIGGER_LEVEL		RX_FIFO_TRIGGER_LEVEL_4_BYTES
+#define TX_FIFO_RESET			DISABLE
+#define RX_FIFO_RESET			DISABLE
+#define FIFO_ENABLE			ENABLE
+#define UFCON_VAL			((TX_FIFO_TRIGGER_LEVEL << 8) \
+					| (RX_FIFO_TRIGGER_LEVEL << 4) \
+					| (TX_FIFO_RESET << 2) \
+					| (RX_FIFO_RESET << 1) \
+					| (FIFO_ENABLE << 0))
+/*
+ * Baud Rate Division Value
+ * 115200 BAUD:
+ * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
+ * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
+ */
+#define UBRDIV_VAL		0x2F
+
+/*
+ * Fractional Part of Baud Rate Divisor:
+ * 115200 BAUD:
+ * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
+ * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
+ */
+#define UFRACVAL_VAL		0x3
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..bb690d6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -217,6 +217,7 @@  s5p_goni                     arm         armv7       goni                samsung
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
 origen			     arm	 armv7	     origen		 samsung	exynos
 s5pc210_universal            arm         armv7       universal_c210      samsung        exynos
+smdk5250		     arm	 armv7	     smdk5250		 samsung	exynos
 smdkv310		     arm	 armv7	     smdkv310		 samsung	exynos
 harmony                      arm         armv7       harmony             nvidia         tegra2
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
new file mode 100644
index 0000000..32e5d7f
--- /dev/null
+++ b/include/configs/smdk5250.h
@@ -0,0 +1,182 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P		1	/* S5P Family */
+#define CONFIG_EXYNOS5		1	/* which is in a Exynos5 Family */
+#define CONFIG_CPU_EXYNOS5250	1	/* which is in a Exynos5250 */
+#define CONFIG_SMDK5250		1	/* which is in a SMDK5250 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF			1
+#define CONFIG_SYS_DCACHE_OFF		1
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250		3774
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_SERIAL1			1	/* use SERIAL 1 */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_S5P_MMC			1
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"SMDK5250 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
+
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH		1
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for SMDK5250"
+
+
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef	CONFIG_SECURE_BL1_ONLY
+#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
+#else
+#define	CONFIG_SEC_FW_SIZE		0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
+#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define MMC_MAX_CHANNEL		5
+
+#endif	/* __CONFIG_H */