| Message ID | 1453824287-37678-1-git-send-email-james.greenhalgh@arm.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote: > > Hi, > > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction > available when compiling with -march=armv8.1-a are only usable with > a register number in the range 0 to 15 for operand 3, as gas will point > out: > > Error: register number out of range 0 to 15 at > operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' > > This patch teaches GCC to avoid registers outside of this range when > appropriate, in the same fashion as we do for other instructions with > this limitation. > > Tested on an internal testsuite targeting Neon intrinsics. > > OK? *ping* Thanks, James > --- > 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com> > > * config/aarch64/aarch64.md > (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register > constraints for operand 3. > (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise. > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index e1f5682..0b46e78 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -3240,7 +3240,7 @@ > [(match_operand:VDQHS 1 "register_operand" "0") > (match_operand:VDQHS 2 "register_operand" "w") > (vec_select:<VEL> > - (match_operand:<VCOND> 3 "register_operand" "w") > + (match_operand:<VCOND> 3 "register_operand" "<vwx>") > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > SQRDMLH_AS))] > "TARGET_SIMD_RDMA" > @@ -3258,7 +3258,7 @@ > [(match_operand:SD_HSI 1 "register_operand" "0") > (match_operand:SD_HSI 2 "register_operand" "w") > (vec_select:<VEL> > - (match_operand:<VCOND> 3 "register_operand" "w") > + (match_operand:<VCOND> 3 "register_operand" "<vwx>") > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > SQRDMLH_AS))] > "TARGET_SIMD_RDMA" > @@ -3278,7 +3278,7 @@ > [(match_operand:VDQHS 1 "register_operand" "0") > (match_operand:VDQHS 2 "register_operand" "w") > (vec_select:<VEL> > - (match_operand:<VCONQ> 3 "register_operand" "w") > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > SQRDMLH_AS))] > "TARGET_SIMD_RDMA" > @@ -3296,7 +3296,7 @@ > [(match_operand:SD_HSI 1 "register_operand" "0") > (match_operand:SD_HSI 2 "register_operand" "w") > (vec_select:<VEL> > - (match_operand:<VCONQ> 3 "register_operand" "w") > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > SQRDMLH_AS))] > "TARGET_SIMD_RDMA"
On Mon, Feb 08, 2016 at 12:52:00PM +0000, James Greenhalgh wrote: > On Tue, Jan 26, 2016 at 04:04:47PM +0000, James Greenhalgh wrote: > > > > Hi, > > > > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction > > available when compiling with -march=armv8.1-a are only usable with > > a register number in the range 0 to 15 for operand 3, as gas will point > > out: > > > > Error: register number out of range 0 to 15 at > > operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' > > > > This patch teaches GCC to avoid registers outside of this range when > > appropriate, in the same fashion as we do for other instructions with > > this limitation. > > > > Tested on an internal testsuite targeting Neon intrinsics. > > > > OK? > > *ping* *ping^2* Thanks, James > > --- > > 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com> > > > > * config/aarch64/aarch64.md > > (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register > > constraints for operand 3. > > (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise. > > > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > > index e1f5682..0b46e78 100644 > > --- a/gcc/config/aarch64/aarch64-simd.md > > +++ b/gcc/config/aarch64/aarch64-simd.md > > @@ -3240,7 +3240,7 @@ > > [(match_operand:VDQHS 1 "register_operand" "0") > > (match_operand:VDQHS 2 "register_operand" "w") > > (vec_select:<VEL> > > - (match_operand:<VCOND> 3 "register_operand" "w") > > + (match_operand:<VCOND> 3 "register_operand" "<vwx>") > > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > > SQRDMLH_AS))] > > "TARGET_SIMD_RDMA" > > @@ -3258,7 +3258,7 @@ > > [(match_operand:SD_HSI 1 "register_operand" "0") > > (match_operand:SD_HSI 2 "register_operand" "w") > > (vec_select:<VEL> > > - (match_operand:<VCOND> 3 "register_operand" "w") > > + (match_operand:<VCOND> 3 "register_operand" "<vwx>") > > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > > SQRDMLH_AS))] > > "TARGET_SIMD_RDMA" > > @@ -3278,7 +3278,7 @@ > > [(match_operand:VDQHS 1 "register_operand" "0") > > (match_operand:VDQHS 2 "register_operand" "w") > > (vec_select:<VEL> > > - (match_operand:<VCONQ> 3 "register_operand" "w") > > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") > > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > > SQRDMLH_AS))] > > "TARGET_SIMD_RDMA" > > @@ -3296,7 +3296,7 @@ > > [(match_operand:SD_HSI 1 "register_operand" "0") > > (match_operand:SD_HSI 2 "register_operand" "w") > > (vec_select:<VEL> > > - (match_operand:<VCONQ> 3 "register_operand" "w") > > + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") > > (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] > > SQRDMLH_AS))] > > "TARGET_SIMD_RDMA" >
On 26 January 2016 at 16:04, James Greenhalgh <james.greenhalgh@arm.com> wrote: > 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com> > > * config/aarch64/aarch64.md > (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register > constraints for operand 3. > (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise. > OK /Marcus
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e1f5682..0b46e78 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3240,7 +3240,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3258,7 +3258,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3278,7 +3278,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3296,7 +3296,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA"
Hi, In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction available when compiling with -march=armv8.1-a are only usable with a register number in the range 0 to 15 for operand 3, as gas will point out: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' This patch teaches GCC to avoid registers outside of this range when appropriate, in the same fashion as we do for other instructions with this limitation. Tested on an internal testsuite targeting Neon intrinsics. OK? Thanks, James --- 2016-01-25 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64.md (arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register constraints for operand 3. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.