| Message ID | 20220912192629.461452-1-horatiu.vultur@microchip.com |
|---|---|
| State | Accepted |
| Commit | f5fc22cbbdcd349402faaddf1a07eb8403658ae8 |
| Headers | show |
| Series | ARM: dts: lan966x: Fix the interrupt number for internal PHYs | expand |
On 12.09.2022 22:26, Horatiu Vultur wrote: > According to the datasheet the interrupts for internal PHYs are > 80 and 81. > > Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes") > Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Applied to at91-fixes, thanks! > --- > arch/arm/boot/dts/lan966x.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > index bcb130a2471d..23665a042990 100644 > --- a/arch/arm/boot/dts/lan966x.dtsi > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -547,13 +547,13 @@ mdio1: mdio@e200413c { > > phy0: ethernet-phy@1 { > reg = <1>; > - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > status = "disabled"; > }; > > phy1: ethernet-phy@2 { > reg = <2>; > - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > status = "disabled"; > }; > };
Am 2022-09-13 09:57, schrieb Horatiu Vultur: >> Accoring to Table 3-155: Shared Peripheral Interrupts >> There are ID47 and ID48 listed as "MIIM controller 0 interrupt". >> Whatever that is, because the internal PHYs are on MIIM >> controller 1. >> >> But 80 and 81 would be ID48 and ID49. Did you test the >> interrupts? > > Looking the same table (3-155) in the documentation that I have these > interrupts correspond to ID112 and ID113 (Embedded CuPHY port 0/1 > interrupt). > And because these are shared peripheral interrupts, it is required to > substract 32. Therefore I got the numbers 80 and 81. Ahh, I need more coffee :) Yes you are right. > As the internal PHYs don't have yet interrupt support, I have sent a > patch here [1] and I have tested it with this. > > [1] https://www.spinics.net/lists/kernel/msg4511731.html Thanks for the pointer! -michael
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index bcb130a2471d..23665a042990 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -547,13 +547,13 @@ mdio1: mdio@e200413c { phy0: ethernet-phy@1 { reg = <1>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; phy1: ethernet-phy@2 { reg = <2>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; };
According to the datasheet the interrupts for internal PHYs are 80 and 81. Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> --- arch/arm/boot/dts/lan966x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)