From patchwork Thu Jan 5 04:25:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 6058 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8130123E01 for ; Thu, 5 Jan 2012 04:27:28 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 77CF0A18269 for ; Thu, 5 Jan 2012 04:27:28 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so115813eaa.11 for ; Wed, 04 Jan 2012 20:27:28 -0800 (PST) Received: by 10.204.156.219 with SMTP id y27mr166819bkw.71.1325737648190; Wed, 04 Jan 2012 20:27:28 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs391023bkc; Wed, 4 Jan 2012 20:27:28 -0800 (PST) Received: by 10.42.131.7 with SMTP id x7mr463690ics.11.1325737645690; Wed, 04 Jan 2012 20:27:25 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id g8si31551517ick.49.2012.01.04.20.27.25 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 20:27:25 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by mail-iy0-f178.google.com with SMTP id f6so340275iag.37 for ; Wed, 04 Jan 2012 20:27:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=x6cA0B8isv5UdDyfYcdT8+7jIbzAbQskuRZNlLhMij0=; b=QLLhW91+92J5fgbzqHM2tnd6THN/QVTlv0PHnPAUIjSIS1dSYLYUjP9WqxO7rf0Pcd T/7xIMpwi1FNHNMobqvYa7KE2PwFJcDgjD3hg8Pm21WoiE71Tryuwpio02qQVsRFMJoT iUmm6p1ajB/2evEA9UfnR/L9f3NJhUozd4QH8= Received: by 10.50.153.133 with SMTP id vg5mr993756igb.8.1325737644960; Wed, 04 Jan 2012 20:27:24 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id rc7sm121098773igb.0.2012.01.04.20.27.22 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 04 Jan 2012 20:27:24 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V5 4/5] ARM: exynos: remove useless code to save/restore L2 Date: Thu, 5 Jan 2012 09:55:24 +0530 Message-Id: <1325737525-12869-5-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1325737525-12869-1-git-send-email-amit.kachhap@linaro.org> References: <1325737525-12869-1-git-send-email-amit.kachhap@linaro.org> Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/pm.c | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a4f61a4..2dd55a1 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -386,13 +378,6 @@ static void exynos4_pm_resume(void) scu_enable(S5P_VA_SCU); -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }