From patchwork Fri Jan 29 08:39:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kefeng Wang X-Patchwork-Id: 60776 Delivered-To: patch@linaro.org Received: by 10.112.130.2 with SMTP id oa2csp972647lbb; Fri, 29 Jan 2016 00:36:08 -0800 (PST) X-Received: by 10.66.158.37 with SMTP id wr5mr11740984pab.48.1454056565509; Fri, 29 Jan 2016 00:36:05 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q80si22779182pfa.60.2016.01.29.00.36.05; Fri, 29 Jan 2016 00:36:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754388AbcA2IgE (ORCPT + 6 others); Fri, 29 Jan 2016 03:36:04 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:52434 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754251AbcA2IgB (ORCPT ); Fri, 29 Jan 2016 03:36:01 -0500 Received: from 172.24.1.50 (EHLO szxeml425-hub.china.huawei.com) ([172.24.1.50]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAQ87032; Fri, 29 Jan 2016 16:35:54 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml425-hub.china.huawei.com (10.82.67.180) with Microsoft SMTP Server id 14.3.235.1; Fri, 29 Jan 2016 16:35:44 +0800 From: Kefeng Wang To: Wei Xu , Mark Rutland , Catalin Marinas , Will Deacon , Rob Herring CC: , , , , Kefeng Wang Subject: [PATCH 4/6] arm64: dts: hip05: Append gpio nodes Date: Fri, 29 Jan 2016 16:39:04 +0800 Message-ID: <1454056746-5048-5-git-send-email-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 2.6.0.GIT In-Reply-To: <1454056746-5048-1-git-send-email-wangkefeng.wang@huawei.com> References: <1454056746-5048-1-git-send-email-wangkefeng.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.56AB246B.002C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 579985196a63e0d5b67b39af812f0cd6 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are two dw GPIO controllers in hip05 peri sub, this patch adds the corresponding device tree nodes. Signed-off-by: Kefeng Wang --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.6.0.GIT -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index c1b1a32..6319ff3 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -322,5 +322,43 @@ reg-io-width = <4>; status = "disabled"; }; + + peri_gpio0: gpio@802e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802e0000 0x0 0x10000>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + peri_gpio1: gpio@802f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802f0000 0x0 0x10000>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; }; };