| Message ID | 20220923121745.129167-2-matthew.gerlach@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/6] Documentation: fpga: dfl: Add documentation for DFHv1 | expand |
On Fri, Sep 23, 2022 at 05:17:40AM -0700, matthew.gerlach@linux.intel.com wrote: > +With DFHv0, the register map of a given feature is located immediately following > +the DFHv0 in the memory space. With DFHv1, the location of the feature register > +map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1 > +structure is shown below: > + > + +-----------------------------------------------------------------------+ > + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| > + +-----------------------------------------------------------------------+ > + |63 GUID_L 0| > + +-----------------------------------------------------------------------+ > + |63 GUID_H 0| > + +-----------------------------------------------------------------------+ > + |63 Address/Offset 1| Rel 0| > + +-----------------------------------------------------------------------+ > + |63 Size of register set 32|Params 31|30 Group 16|15 Instance 0| > + +-----------------------------------------------------------------------+ > + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| > + +-----------------------------------------------------------------------+ > + |63 Parameter Data 0| > + +-----------------------------------------------------------------------+ > + > + ... > + > + +-----------------------------------------------------------------------+ > + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| > + +-----------------------------------------------------------------------+ > + |63 Parameter Data 0| > + +-----------------------------------------------------------------------+ > + For consistency with DFL location diagram (which is above the DFHv1 diagram above), use literal code block instead of table: ---- >8 ---- diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 7c786b75b4988f..db6bff4aee25eb 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -584,7 +584,7 @@ across all types. With DFHv0, the register map of a given feature is located immediately following the DFHv0 in the memory space. With DFHv1, the location of the feature register map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1 -structure is shown below: +structure is shown below:: +-----------------------------------------------------------------------+ |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| Thanks.
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 15b670926084..7c786b75b498 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -561,6 +561,55 @@ new DFL feature via UIO direct access, its feature id should be added to the driver's id_table. +Extending the Device Feature Header - DFHv1 +=========================================== +The current 8 bytes of the Device Feature Header, hereafter referred to as +to DFHv0, provide very little opportunity for the hardware to describe itself +to software. Version 1 of the Device Feature Header (DFHv1) is being introduced +to provide increased flexibility and extensibility to hardware designs using +Device Feature Lists. The list below describes some of the goals behind the +changes in DFHv1: + +* Provide a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouple the location of the DFH from the register space of the feature itself. + +Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate +a list of parameter values to a particular feature. + +With DFHv0, not all features types contained a GUID. DFHv1 makes the GUID standard +across all types. + +With DFHv0, the register map of a given feature is located immediately following +the DFHv0 in the memory space. With DFHv1, the location of the feature register +map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1 +structure is shown below: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| + +-----------------------------------------------------------------------+ + |63 GUID_L 0| + +-----------------------------------------------------------------------+ + |63 GUID_H 0| + +-----------------------------------------------------------------------+ + |63 Address/Offset 1| Rel 0| + +-----------------------------------------------------------------------+ + |63 Size of register set 32|Params 31|30 Group 16|15 Instance 0| + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration