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[209.132.180.67]) by mx.google.com with ESMTP id n16si630810pfa.122.2016.02.01.07.09.18; Mon, 01 Feb 2016 07:09:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933298AbcBAPJQ (ORCPT + 30 others); Mon, 1 Feb 2016 10:09:16 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:32984 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753961AbcBAPIX (ORCPT ); Mon, 1 Feb 2016 10:08:23 -0500 Received: by mail-wm0-f43.google.com with SMTP id l66so74759569wml.0 for ; Mon, 01 Feb 2016 07:08:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26yxjHu6OBvG/ZCYCuUO9nI1JNT01mFBjnzHcae5qKs=; b=Y4rG2Xbf8UX7JXzpgAVkbpM6oj2ffvv7HTXS5R/r0eJVYLo2IFZFSzNs+hUOPMzle4 H8LkjRCTLw4FwTK86ns+CtPUF4bwDTFzOza9i1ULFfLiawN8yRQzBKllncYjNOWb3qLz KEFb4adDGgMxUTq1DDv29s3p0u/evxaAAthmA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26yxjHu6OBvG/ZCYCuUO9nI1JNT01mFBjnzHcae5qKs=; b=DciaQNZivgZPYmwRZxY++r/VYh444H4J0pSonjFiq3DrALH7nzHli1V5hqxrYzhB1s rhR0L29kW72jLVGv00Kq6I112pHKK8q0nUFvW/zO8rGMr84Mvw2PvC93vRfBUoeQHW+m jhL1q/VkHTEA0ONb++Y2s1FlUmYSl63WzwhXeSpWegrZCPoM9Bmpao5AwIqOf+Yc3hZb ezJiAdj8tMaPpWNxm8Oj1LX8WbndC9L3HwbI7jvY4uWo9jQpma/oScAfXkXtWEsfsETf Ml0L5S6fC2OE5Zxduvh+j7dF5EraxxIGcBxHNDxnNkCnHBzljMyBEqK9XBsdSLpy60lt fa0g== X-Gm-Message-State: AG10YOQM5ROiL7Md832lIeXN9OaZLuyRNAxVPfzxEhHwm/ANMhkCU+SUapMSHjovQ3LpkUZM X-Received: by 10.194.201.134 with SMTP id ka6mr23214006wjc.116.1454339302453; Mon, 01 Feb 2016 07:08:22 -0800 (PST) Received: from mms.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.googlemail.com with ESMTPSA id qs1sm29444930wjc.2.2016.02.01.07.08.21 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Feb 2016 07:08:21 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 1/3] clk: qcom: Add A53 PLL support Date: Mon, 1 Feb 2016 17:07:49 +0200 Message-Id: <1454339271-643-2-git-send-email-georgi.djakov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1454339271-643-1-git-send-email-georgi.djakov@linaro.org> References: <1454339271-643-1-git-send-email-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the PLL, which generates the higher range of CPU frequencies on MSM8916 platforms. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53-pll.txt | 17 ++++ drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 95 ++++++++++++++++++++ 4 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53-pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c diff --git a/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt new file mode 100644 index 000000000000..50e71e4e13a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53-pll.txt @@ -0,0 +1,17 @@ +A53 PLL Binding +--------------- +The A53 PLL is the main CPU PLL used for frequencies above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,a53-pll" + +- reg : shall contain base register location and length + +Example: + + a53pll: a53pll@0b016000 { + compatible = "qcom,a53-pll"; + reg = <0x0b016000 0x40>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b552eceec2be..d06cf687be4f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -123,3 +123,12 @@ config MSM_MMCC_8996 Support for the multimedia clock controller on msm8996 devices. Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. + +config QCOM_A53PLL + bool "A53 PLL" + depends on COMMON_CLK_QCOM + help + Support for the A53 PLL on some Qualcomm devices. It provides + support for CPU frequencies above 1GHz. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dc4280b85db1..c7c26eeab67c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..987bf75f087a --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016, Linaro Limited. All rights reserved. + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 65, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,a53-pll" }, + { } +}; + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_pll *pll; + struct resource *res; + void __iomem *base; + struct clk *clk; + struct regmap *regmap; + struct clk_init_data init; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04, + pll->m_reg = 0x08, + pll->n_reg = 0x0c, + pll->config_reg = 0x14, + pll->mode_reg = 0x00, + pll->status_reg = 0x1c, + pll->status_bit = 16, + pll->freq_tbl = a53pll_freq, + + init.name = "a53pll", + init.parent_names = (const char *[]){ "xo" }, + init.num_parents = 1, + init.ops = &clk_pll_sr2_ops, + pll->clkr.hw.init = &init; + + clk = devm_clk_register_regmap(dev, &pll->clkr); + + return PTR_ERR_OR_ZERO(clk); +} + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver);