diff mbox series

[v8,1/2] dt-bindings: mips: add CPU bindings for MIPS architecture

Message ID 20221006042945.1038594-2-sergio.paracuellos@gmail.com
State Accepted
Commit c8dabef8643bd0b88087c0280ccf555ba8d45087
Headers show
Series [v8,1/2] dt-bindings: mips: add CPU bindings for MIPS architecture | expand

Commit Message

Sergio Paracuellos Oct. 6, 2022, 4:29 a.m. UTC
Add the yaml binding for available CPUs in MIPS architecture.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 .../bindings/mips/brcm/brcm,bmips.txt         |   8 --
 .../devicetree/bindings/mips/cpus.yaml        | 115 ++++++++++++++++++
 .../bindings/mips/ingenic/ingenic,cpu.yaml    |  69 -----------
 3 files changed, 115 insertions(+), 77 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
 create mode 100644 Documentation/devicetree/bindings/mips/cpus.yaml
 delete mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml

Comments

Sergio Paracuellos Oct. 21, 2022, 9:05 a.m. UTC | #1
On Fri, Oct 21, 2022 at 11:02 AM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Mon, Oct 17, 2022 at 07:53:00AM +0200, Sergio Paracuellos wrote:
> > On Thu, Oct 6, 2022 at 1:24 PM Philippe Mathieu-Daudé
> > <philmd@fungible.com> wrote:
> > >
> > > On 6/10/22 06:29, Sergio Paracuellos wrote:
> > > > Add the yaml binding for available CPUs in MIPS architecture.
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > > > ---
> > > >   .../bindings/mips/brcm/brcm,bmips.txt         |   8 --
> > > >   .../devicetree/bindings/mips/cpus.yaml        | 115 ++++++++++++++++++
> > > >   .../bindings/mips/ingenic/ingenic,cpu.yaml    |  69 -----------
> > > >   3 files changed, 115 insertions(+), 77 deletions(-)
> > > >   delete mode 100644 Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
> > > >   create mode 100644 Documentation/devicetree/bindings/mips/cpus.yaml
> > > >   delete mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
> > >
> > > Reviewed-by: Philippe Mathieu-Daudé <philmd@fungible.com>
> >
> > Thanks!
> >
> > Thomas, are this series going through your tree?
>
> I'll take them.

Thanks for letting me know!!

>
> Thomas.
>

Best regards,
    Sergio Paracuellos


> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]
Sergio Paracuellos Nov. 11, 2022, 4:33 p.m. UTC | #2
On Fri, Oct 21, 2022 at 11:05 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> On Fri, Oct 21, 2022 at 11:02 AM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
> >
> > On Mon, Oct 17, 2022 at 07:53:00AM +0200, Sergio Paracuellos wrote:
> > > On Thu, Oct 6, 2022 at 1:24 PM Philippe Mathieu-Daudé
> > > <philmd@fungible.com> wrote:
> > > >
> > > > On 6/10/22 06:29, Sergio Paracuellos wrote:
> > > > > Add the yaml binding for available CPUs in MIPS architecture.
> > > > >
> > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > > > > ---
> > > > >   .../bindings/mips/brcm/brcm,bmips.txt         |   8 --
> > > > >   .../devicetree/bindings/mips/cpus.yaml        | 115 ++++++++++++++++++
> > > > >   .../bindings/mips/ingenic/ingenic,cpu.yaml    |  69 -----------
> > > > >   3 files changed, 115 insertions(+), 77 deletions(-)
> > > > >   delete mode 100644 Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
> > > > >   create mode 100644 Documentation/devicetree/bindings/mips/cpus.yaml
> > > > >   delete mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
> > > >
> > > > Reviewed-by: Philippe Mathieu-Daudé <philmd@fungible.com>
> > >
> > > Thanks!
> > >
> > > Thomas, are this series going through your tree?
> >
> > I'll take them.
>
> Thanks for letting me know!!

It’s been a while and this series is still not added to the mips tree…
Gentle ping :)

Thanks!!

Best regards,
    Sergio Paracuellos

>
> >
> > Thomas.
> >
>
> Best regards,
>     Sergio Paracuellos
>
>
> > --
> > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> > good idea.                                                [ RFC1925, 2.3 ]
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt b/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
deleted file mode 100644
index 8ef71b4085ca..000000000000
--- a/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
+++ /dev/null
@@ -1,8 +0,0 @@ 
-* Broadcom MIPS (BMIPS) CPUs
-
-Required properties:
-- compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380",
-  "brcm,bmips5000"
-
-- mips-hpt-frequency: This is common to all CPUs in the system so it lives
-  under the "cpus" node.
diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
new file mode 100644
index 000000000000..e991f4c6668d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cpus.yaml
@@ -0,0 +1,115 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS CPUs bindings
+
+maintainers:
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+
+description: |
+  The device tree allows to describe the layout of CPUs in a system through
+  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+  defining properties for every CPU.
+
+properties:
+  compatible:
+    enum:
+      - brcm,bmips3300
+      - brcm,bmips4350
+      - brcm,bmips4380
+      - brcm,bmips5000
+      - brcm,bmips5200
+      - ingenic,xburst-mxu1.0
+      - ingenic,xburst-fpu1.0-mxu1.1
+      - ingenic,xburst-fpu2.0-mxu2.0
+      - ingenic,xburst2-fpu2.1-mxu2.1-smt
+      - loongson,gs264
+      - mips,m14Kc
+      - mips,mips4Kc
+      - mips,mips4KEc
+      - mips,mips24Kc
+      - mips,mips24KEc
+      - mips,mips74Kc
+      - mips,mips1004Kc
+      - mti,interaptiv
+      - mti,mips24KEc
+      - mti,mips14KEc
+      - mti,mips14Kc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  device_type: true
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ingenic,xburst-mxu1.0
+              - ingenic,xburst-fpu1.0-mxu1.1
+              - ingenic,xburst-fpu2.0-mxu2.0
+              - ingenic,xburst2-fpu2.1-mxu2.1-smt
+    then:
+      required:
+        - device_type
+        - clocks
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    cpus {
+      #size-cells = <0>;
+      #address-cells = <1>;
+
+      cpu@0 {
+        compatible = "mips,mips1004Kc";
+        device_type = "cpu";
+        reg = <0>;
+      };
+
+      cpu@1 {
+        compatible = "mips,mips1004Kc";
+        device_type = "cpu";
+        reg = <1>;
+      };
+    };
+
+  - |
+    // Example 2 (Ingenic CPU)
+    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
+
+    cpus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      cpu@0 {
+        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+        device_type = "cpu";
+        reg = <0>;
+
+        clocks = <&cgu JZ4780_CLK_CPU>;
+      };
+
+      cpu@1 {
+        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+        device_type = "cpu";
+        reg = <1>;
+
+        clocks = <&cgu JZ4780_CLK_CORE1>;
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
deleted file mode 100644
index b7e7fa715437..000000000000
--- a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
+++ /dev/null
@@ -1,69 +0,0 @@ 
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Bindings for Ingenic XBurst family CPUs
-
-maintainers:
-  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
-
-description:
-  Ingenic XBurst family CPUs shall have the following properties.
-
-properties:
-  compatible:
-    oneOf:
-
-      - description: Ingenic XBurst®1 CPU Cores
-        enum:
-          - ingenic,xburst-mxu1.0
-          - ingenic,xburst-fpu1.0-mxu1.1
-          - ingenic,xburst-fpu2.0-mxu2.0
-
-      - description: Ingenic XBurst®2 CPU Cores
-        enum:
-          - ingenic,xburst2-fpu2.1-mxu2.1-smt
-
-  reg:
-    maxItems: 1
-
-  clocks:
-    maxItems: 1
-
-  device_type: true
-
-required:
-  - device_type
-  - compatible
-  - reg
-  - clocks
-
-additionalProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
-
-    cpus {
-        #address-cells = <1>;
-        #size-cells = <0>;
-
-        cpu0: cpu@0 {
-                device_type = "cpu";
-                compatible = "ingenic,xburst-fpu1.0-mxu1.1";
-                reg = <0>;
-
-                clocks = <&cgu JZ4780_CLK_CPU>;
-        };
-
-        cpu1: cpu@1 {
-                device_type = "cpu";
-                compatible = "ingenic,xburst-fpu1.0-mxu1.1";
-                reg = <1>;
-
-                clocks = <&cgu JZ4780_CLK_CORE1>;
-        };
-    };
-...