| Message ID | 20221010162248.348141-5-Perry.Yuan@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | Implement AMD Pstate EPP Driver | expand |
On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > This MSR can be used to check whether the CPU frequency boost state > is enabled in the hardware control. User can change the boost state in > the BIOS setting,amd_pstate driver will update the boost state according > to this msr value. > > AMD Processor Programming Reference (PPR) > Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] > Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162] > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > --- > arch/x86/include/asm/msr-index.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 6674bdb096f3..e5ea1c9f747b 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -569,6 +569,7 @@ > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > #define MSR_AMD_CPPC_REQ 0xc00102b3 > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > @@ -579,6 +580,8 @@ > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > +#define AMD_CPPC_PRECISION_BOOST_ENABLED BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with MSR_K7_HWCR https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ Could you please make sure address the commments? Thanks, Ray
[Public] > -----Original Message----- > From: Limonciello, Mario <Mario.Limonciello@amd.com> > Sent: Friday, October 21, 2022 12:05 AM > To: Yuan, Perry <Perry.Yuan@amd.com>; Huang, Ray > <Ray.Huang@amd.com> > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, Deepak > <Deepak.Sharma@amd.com>; Fontenot, Nathan > <Nathan.Fontenot@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > AMD CPPC boost state > > [Public] > > > > > -----Original Message----- > > From: Yuan, Perry <Perry.Yuan@amd.com> > > Sent: Thursday, October 20, 2022 11:01 > > To: Huang, Ray <Ray.Huang@amd.com> > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > kernel@vger.kernel.org > > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > > AMD CPPC boost state > > > > [AMD Official Use Only - General] > > > > Hi Ray. > > > > > -----Original Message----- > > > From: Huang, Ray <Ray.Huang@amd.com> > > > Sent: Monday, October 17, 2022 5:57 PM > > > To: Yuan, Perry <Perry.Yuan@amd.com> > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; > > > Du, Xiaojian <Xiaojian.Du@amd.com>; > > Meng, > > > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > kernel@vger.kernel.org > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > for AMD CPPC boost state > > > > > > On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > > > > This MSR can be used to check whether the CPU frequency boost > > > > state is enabled in the hardware control. User can change the > > > > boost state in the BIOS setting,amd_pstate driver will update the > > > > boost state according to this msr value. > > > > > > > > AMD Processor Programming Reference (PPR) > > > > Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] > > > > Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip > > > > [p162] > > > > > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > > > > --- > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > 1 file changed, 3 insertions(+) > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h > > > > b/arch/x86/include/asm/msr-index.h > > > > index 6674bdb096f3..e5ea1c9f747b 100644 > > > > --- a/arch/x86/include/asm/msr-index.h > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > @@ -569,6 +569,7 @@ > > > > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > > > > #define MSR_AMD_CPPC_REQ 0xc00102b3 > > > > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > > > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > > > > > > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) > > > > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > > > @@ -579,6 +580,8 @@ > > > > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > > > > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > > > > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > > > > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > > > > +#define AMD_CPPC_PRECISION_BOOST_ENABLED > > > BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) > > > > > > I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with > > > MSR_K7_HWCR > > > > > > https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ > > > https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ > > > > > > Could you please make sure address the commments? > > > > > > Thanks, > > > Ray > > > > If I rename that the MSR definition string, that will cause lots of > > driver file change. > > So I suggest to add one new MSR macro for the CPPC, the MSR_K7_HWCR is > > mismatching in the CPPC Pstate driver. > > If you refuse to use this new one, I will reuse that old one. > > To avoid changing too much stuff at once how about if you give an alias? > IE something like: > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR I prefer this code suggestion. Then the new name string can be matched with CPPC/Pstate driver. > > > > > Perry.
[AMD Official Use Only - General] Hi Ray. > -----Original Message----- > From: Huang, Ray <Ray.Huang@amd.com> > Sent: Friday, October 21, 2022 1:22 PM > To: Limonciello, Mario <Mario.Limonciello@amd.com> > Cc: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>; > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > kernel@vger.kernel.org; Borislav Petkov <bp@alien8.de> > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > AMD CPPC boost state > > + Boris, > > On Fri, Oct 21, 2022 at 12:05:21AM +0800, Limonciello, Mario wrote: > > [Public] > > > > > > > > > -----Original Message----- > > > From: Yuan, Perry <Perry.Yuan@amd.com> > > > Sent: Thursday, October 20, 2022 11:01 > > > To: Huang, Ray <Ray.Huang@amd.com> > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; > > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) > > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > kernel@vger.kernel.org > > > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > for AMD CPPC boost state > > > > > > [AMD Official Use Only - General] > > > > > > Hi Ray. > > > > > > > -----Original Message----- > > > > From: Huang, Ray <Ray.Huang@amd.com> > > > > Sent: Monday, October 17, 2022 5:57 PM > > > > To: Yuan, Perry <Perry.Yuan@amd.com> > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > > > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; > > > Meng, > > > > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > > kernel@vger.kernel.org > > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > > for AMD CPPC boost state > > > > > > > > On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > > > > > This MSR can be used to check whether the CPU frequency boost > > > > > state is enabled in the hardware control. User can change the > > > > > boost state in the BIOS setting,amd_pstate driver will update > > > > > the boost state according to this msr value. > > > > > > > > > > AMD Processor Programming Reference (PPR) > > > > > Link: https://www.amd.com/system/files/TechDocs/40332.pdf > > > > > [p1095] > > > > > Link: https://www.amd.com/system/files/TechDocs/56569-A1- > PUB.zip > > > > > [p162] > > > > > > > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > > > > > --- > > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h > > > > > b/arch/x86/include/asm/msr-index.h > > > > > index 6674bdb096f3..e5ea1c9f747b 100644 > > > > > --- a/arch/x86/include/asm/msr-index.h > > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > > @@ -569,6 +569,7 @@ > > > > > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > > > > > #define MSR_AMD_CPPC_REQ 0xc00102b3 > > > > > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > > > > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > > > > > > > > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) > > > > > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > > > > @@ -579,6 +580,8 @@ > > > > > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > > > > > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > > > > > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > > > > > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > > > > > +#define AMD_CPPC_PRECISION_BOOST_ENABLED > > > > BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) > > > > > > > > I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with > > > > MSR_K7_HWCR > > > > > > > > https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ > > > > https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ > > > > > > > > Could you please make sure address the commments? > > > > > > > > Thanks, > > > > Ray > > > > > > If I rename that the MSR definition string, that will cause lots of > > > driver file change. > > > So I suggest to add one new MSR macro for the CPPC, the MSR_K7_HWCR > > > is mismatching in the CPPC Pstate driver. > > > If you refuse to use this new one, I will reuse that old one. > > > > To avoid changing too much stuff at once how about if you give an alias? > > IE something like: > > > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR > > > > The mainly concern is that HWCR is for legacy ACPI P-State control not for > CPPC. I talked with hardware guys before, it's not suggested to mix them up > together. This register has been defined for a long time even before Zen > processor. > > Thanks, > Ray I have removed the code not to write boost state to that MSR, just check the boost state from the MSR bit value. It will not cause any problems, I have tested and confirmed that the BIT value will be changed after BOOST ON/OFF switched in BIOS setting. So we can just check the boost state here for pstate driver notification. Perry.
[AMD Official Use Only - General] Hi Boris. > -----Original Message----- > From: Borislav Petkov <bp@alien8.de> > Sent: Friday, October 21, 2022 5:38 PM > To: Huang, Ray <Ray.Huang@amd.com> > Cc: Limonciello, Mario <Mario.Limonciello@amd.com>; Yuan, Perry > <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>; > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > AMD CPPC boost state > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > On Fri, Oct 21, 2022 at 01:22:11PM +0800, Huang Rui wrote: > > > > If I rename that the MSR definition string, that will cause lots > > > > of driver file change. > > > > So I suggest to add one new MSR macro for the CPPC, the > > > > MSR_K7_HWCR is mismatching in the CPPC Pstate driver. > > > > If you refuse to use this new one, I will reuse that old one. > > > > > > To avoid changing too much stuff at once how about if you give an alias? > > > IE something like: > > > > > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR > > Why would you all even think about adding a new name and not use > MSR_K7_HWCR? > > The other code uses it just fine, do git grep MSR_K7_HWCR. > > We have waaay too many MSRs, no need to unnecessarily confuse people > with an alias or rename stuff. Just use MSR_K7_HWCR like everything else > does. > > -- > Regards/Gruss, > Boris. > Sure, we can continue to use that MSR definition as you suggested. Thank you comment on this. Perry. > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeop > le.kernel.org%2Ftglx%2Fnotes-about- > netiquette&data=05%7C01%7CPerry.Yuan%40amd.com%7Ce3d156c553 > 2a490a2f2d08dab347f1e8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 > C0%7C638019418849896672%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C > %7C%7C&sdata=wVEYx3BNksqXxaycPl81BjVotrWMlcJnVNdbFO7bQto% > 3D&reserved=0
On Mon, Oct 24, 2022 at 10:56:50AM +0800, Yuan, Perry wrote: > [AMD Official Use Only - General] > > Hi Ray. > > > -----Original Message----- > > From: Huang, Ray <Ray.Huang@amd.com> > > Sent: Friday, October 21, 2022 1:22 PM > > To: Limonciello, Mario <Mario.Limonciello@amd.com> > > Cc: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; > > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>; > > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, > > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > kernel@vger.kernel.org; Borislav Petkov <bp@alien8.de> > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > > AMD CPPC boost state > > > > + Boris, > > > > On Fri, Oct 21, 2022 at 12:05:21AM +0800, Limonciello, Mario wrote: > > > [Public] > > > > > > > > > > > > > -----Original Message----- > > > > From: Yuan, Perry <Perry.Yuan@amd.com> > > > > Sent: Thursday, October 20, 2022 11:01 > > > > To: Huang, Ray <Ray.Huang@amd.com> > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > <Shimmer.Huang@amd.com>; > > > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) > > > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > > kernel@vger.kernel.org > > > > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > > for AMD CPPC boost state > > > > > > > > [AMD Official Use Only - General] > > > > > > > > Hi Ray. > > > > > > > > > -----Original Message----- > > > > > From: Huang, Ray <Ray.Huang@amd.com> > > > > > Sent: Monday, October 17, 2022 5:57 PM > > > > > To: Yuan, Perry <Perry.Yuan@amd.com> > > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > > > > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; > > > > Meng, > > > > > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > > > kernel@vger.kernel.org > > > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > > > for AMD CPPC boost state > > > > > > > > > > On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > > > > > > This MSR can be used to check whether the CPU frequency boost > > > > > > state is enabled in the hardware control. User can change the > > > > > > boost state in the BIOS setting,amd_pstate driver will update > > > > > > the boost state according to this msr value. > > > > > > > > > > > > AMD Processor Programming Reference (PPR) > > > > > > Link: https://www.amd.com/system/files/TechDocs/40332.pdf > > > > > > [p1095] > > > > > > Link: https://www.amd.com/system/files/TechDocs/56569-A1- > > PUB.zip > > > > > > [p162] > > > > > > > > > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > > > > > > --- > > > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h > > > > > > b/arch/x86/include/asm/msr-index.h > > > > > > index 6674bdb096f3..e5ea1c9f747b 100644 > > > > > > --- a/arch/x86/include/asm/msr-index.h > > > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > > > @@ -569,6 +569,7 @@ > > > > > > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > > > > > > #define MSR_AMD_CPPC_REQ 0xc00102b3 > > > > > > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > > > > > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > > > > > > > > > > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) > > > > > > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > > > > > @@ -579,6 +580,8 @@ > > > > > > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > > > > > > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > > > > > > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > > > > > > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > > > > > > +#define AMD_CPPC_PRECISION_BOOST_ENABLED > > > > > BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) > > > > > > > > > > I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with > > > > > MSR_K7_HWCR > > > > > > > > > > https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ > > > > > https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ > > > > > > > > > > Could you please make sure address the commments? > > > > > > > > > > Thanks, > > > > > Ray > > > > > > > > If I rename that the MSR definition string, that will cause lots of > > > > driver file change. > > > > So I suggest to add one new MSR macro for the CPPC, the MSR_K7_HWCR > > > > is mismatching in the CPPC Pstate driver. > > > > If you refuse to use this new one, I will reuse that old one. > > > > > > To avoid changing too much stuff at once how about if you give an alias? > > > IE something like: > > > > > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR > > > > > > > The mainly concern is that HWCR is for legacy ACPI P-State control not for > > CPPC. I talked with hardware guys before, it's not suggested to mix them up > > together. This register has been defined for a long time even before Zen > > processor. > > > > Thanks, > > Ray > > I have removed the code not to write boost state to that MSR, just check the boost state from the MSR bit value. > It will not cause any problems, I have tested and confirmed that the BIT value will be changed after BOOST ON/OFF switched in BIOS setting. > So we can just check the boost state here for pstate driver notification. > If we found MSR_K7_HWCR would impact the max frequency in CPPC, we should report a defect or issue to firmware team. (Then we can add a quirk function to workaround this in amd-pstate) Thanks, Ray
[AMD Official Use Only - General] Hi Ray. > -----Original Message----- > From: Huang, Ray <Ray.Huang@amd.com> > Sent: Tuesday, October 25, 2022 8:32 AM > To: Yuan, Perry <Perry.Yuan@amd.com> > Cc: Limonciello, Mario <Mario.Limonciello@amd.com>; > rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, Deepak > <Deepak.Sharma@amd.com>; Fontenot, Nathan > <Nathan.Fontenot@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > kernel@vger.kernel.org; Borislav Petkov <bp@alien8.de> > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > AMD CPPC boost state > > On Mon, Oct 24, 2022 at 10:56:50AM +0800, Yuan, Perry wrote: > > [AMD Official Use Only - General] > > > > Hi Ray. > > > > > -----Original Message----- > > > From: Huang, Ray <Ray.Huang@amd.com> > > > Sent: Friday, October 21, 2022 1:22 PM > > > To: Limonciello, Mario <Mario.Limonciello@amd.com> > > > Cc: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; > > > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>; > > > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; > > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) > > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > kernel@vger.kernel.org; Borislav Petkov <bp@alien8.de> > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > for AMD CPPC boost state > > > > > > + Boris, > > > > > > On Fri, Oct 21, 2022 at 12:05:21AM +0800, Limonciello, Mario wrote: > > > > [Public] > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > From: Yuan, Perry <Perry.Yuan@amd.com> > > > > > Sent: Thursday, October 20, 2022 11:01 > > > > > To: Huang, Ray <Ray.Huang@amd.com> > > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > > > Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > > <Shimmer.Huang@amd.com>; > > > > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) > > > > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux- > > > > > kernel@vger.kernel.org > > > > > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR > > > > > definition for AMD CPPC boost state > > > > > > > > > > [AMD Official Use Only - General] > > > > > > > > > > Hi Ray. > > > > > > > > > > > -----Original Message----- > > > > > > From: Huang, Ray <Ray.Huang@amd.com> > > > > > > Sent: Monday, October 17, 2022 5:57 PM > > > > > > To: Yuan, Perry <Perry.Yuan@amd.com> > > > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; > > > > > > Sharma, Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario > > > > > > <Mario.Limonciello@amd.com>; Fontenot, Nathan > > > > > > <Nathan.Fontenot@amd.com>; Deucher, Alexander > > > > > > <Alexander.Deucher@amd.com>; Huang, Shimmer > > > > > > <Shimmer.Huang@amd.com>; Du, Xiaojian > <Xiaojian.Du@amd.com>; > > > > > Meng, > > > > > > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; > > > > > > linux- kernel@vger.kernel.org > > > > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR > > > > > > definition for AMD CPPC boost state > > > > > > > > > > > > On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > > > > > > > This MSR can be used to check whether the CPU frequency > > > > > > > boost state is enabled in the hardware control. User can > > > > > > > change the boost state in the BIOS setting,amd_pstate driver > > > > > > > will update the boost state according to this msr value. > > > > > > > > > > > > > > AMD Processor Programming Reference (PPR) > > > > > > > Link: https://www.amd.com/system/files/TechDocs/40332.pdf > > > > > > > [p1095] > > > > > > > Link: https://www.amd.com/system/files/TechDocs/56569-A1- > > > PUB.zip > > > > > > > [p162] > > > > > > > > > > > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > > > > > > > --- > > > > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h > > > > > > > b/arch/x86/include/asm/msr-index.h > > > > > > > index 6674bdb096f3..e5ea1c9f747b 100644 > > > > > > > --- a/arch/x86/include/asm/msr-index.h > > > > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > > > > @@ -569,6 +569,7 @@ > > > > > > > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > > > > > > > #define MSR_AMD_CPPC_REQ 0xc00102b3 > > > > > > > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > > > > > > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > > > > > > > > > > > > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & > 0xff) > > > > > > > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > > > > > > @@ -579,6 +580,8 @@ > > > > > > > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > > > > > > > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > > > > > > > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) > << 24) > > > > > > > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > > > > > > > +#define AMD_CPPC_PRECISION_BOOST_ENABLED > > > > > > BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) > > > > > > > > > > > > I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with > > > > > > MSR_K7_HWCR > > > > > > > > > > > > https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ > > > > > > https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ > > > > > > > > > > > > Could you please make sure address the commments? > > > > > > > > > > > > Thanks, > > > > > > Ray > > > > > > > > > > If I rename that the MSR definition string, that will cause lots > > > > > of driver file change. > > > > > So I suggest to add one new MSR macro for the CPPC, the > > > > > MSR_K7_HWCR is mismatching in the CPPC Pstate driver. > > > > > If you refuse to use this new one, I will reuse that old one. > > > > > > > > To avoid changing too much stuff at once how about if you give an alias? > > > > IE something like: > > > > > > > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR > > > > > > > > > > The mainly concern is that HWCR is for legacy ACPI P-State control > > > not for CPPC. I talked with hardware guys before, it's not suggested > > > to mix them up together. This register has been defined for a long > > > time even before Zen processor. > > > > > > Thanks, > > > Ray > > > > I have removed the code not to write boost state to that MSR, just check > the boost state from the MSR bit value. > > It will not cause any problems, I have tested and confirmed that the BIT > value will be changed after BOOST ON/OFF switched in BIOS setting. > > So we can just check the boost state here for pstate driver notification. > > > > If we found MSR_K7_HWCR would impact the max frequency in CPPC, we > should report a defect or issue to firmware team. (Then we can add a quirk > function to workaround this in amd-pstate) > > Thanks, > Ray Sure , I will revise the patch and still using the MSR_K7_HWCR to check freq boost state in pstate driver. Thanks for the feedback. Perry.
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6674bdb096f3..e5ea1c9f747b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -569,6 +569,7 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) @@ -579,6 +580,8 @@ #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) +#define AMD_CPPC_PRECISION_BOOST_BIT 25 +#define AMD_CPPC_PRECISION_BOOST_ENABLED BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) /* AMD Performance Counter Global Status and Control MSRs */ #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
This MSR can be used to check whether the CPU frequency boost state is enabled in the hardware control. User can change the boost state in the BIOS setting,amd_pstate driver will update the boost state according to this msr value. AMD Processor Programming Reference (PPR) Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162] Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+)