From patchwork Fri Feb 12 08:13:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Auger Eric X-Patchwork-Id: 61831 Delivered-To: patches@linaro.org Received: by 10.112.43.199 with SMTP id y7csp676847lbl; Fri, 12 Feb 2016 00:14:42 -0800 (PST) X-Received: by 10.194.61.104 with SMTP id o8mr212910wjr.67.1455264877445; Fri, 12 Feb 2016 00:14:37 -0800 (PST) Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com. [2a00:1450:400c:c09::232]) by mx.google.com with ESMTPS id kq9si17721749wjc.90.2016.02.12.00.14.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Feb 2016 00:14:37 -0800 (PST) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::232 as permitted sender) client-ip=2a00:1450:400c:c09::232; Authentication-Results: mx.google.com; spf=pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::232 as permitted sender) smtp.mailfrom=eric.auger@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-wm0-x232.google.com with SMTP id c200so9163063wme.0 for ; Fri, 12 Feb 2016 00:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RWEO7BZjiO141e212eVuO6jwWruS6pnKguk05Kd81hs=; b=Aex3j2GG/0kKLwMom7zBqN5+L80ufiuAxy5ouVhIU1+lTY7JST+1BwoVlAV2mOO80k rGGRZYs38PMtubJKKzzuLfI9GZCilisT8gUpuCyEyxOB0m1Ezy+Ez+1Y4Cu+3iNhjGDk O6za+neU+7zRIx6FvX4rKT1xpEeU1l8HPzdbc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RWEO7BZjiO141e212eVuO6jwWruS6pnKguk05Kd81hs=; b=Ht45yJVSb0saoaSPfir5LNvswh7O5kmA4gk0qOwYAABWMHnsc7YdoEIKyiownFpXZ7 GmSqz3VB6zQdPfCuhiuGD075DWuQlOuBjQS2AGojX0S6SC4zPCUU3aWJ49+vuCrykmb/ Y68DFAzUI17x07+CfYHr8W48h1dr0phHftlJMinGpjE2RbAwRPO6VW+JS8bT0MMzoL0B MW/jS0yJGmOd9MXt6njgMVyMVNjUbe2s+14Ztg5us0mOEqwNfkqsYJ2hs2qlj/tiDXz3 AiT4fF6MwvS1uVjTuH9ttPnks3AOxtDhbgz98CxW2K1o6RoXbe6ETQ7rYSXimL3Ddhyr FANA== X-Gm-Message-State: AG10YORgMpx9e+RCvFDF5sKxuMcOuHgl/Zrr2JwyTvrNrUjy133Xa9mGdRkplxvLSHXpDB/GIyU= X-Received: by 10.195.13.68 with SMTP id ew4mr210029wjd.85.1455264877230; Fri, 12 Feb 2016 00:14:37 -0800 (PST) Return-Path: Received: from new-host-17.home (LMontsouris-657-1-37-90.w80-11.abo.wanadoo.fr. [80.11.198.90]) by smtp.gmail.com with ESMTPSA id x66sm1243977wmb.20.2016.02.12.00.14.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Feb 2016 00:14:35 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: suravee.suthikulpanit@amd.com, patches@linaro.org, linux-kernel@vger.kernel.org, Manish.Jaggi@caviumnetworks.com, Bharat.Bhushan@freescale.com, pranav.sawargaonkar@gmail.com, p.fedin@samsung.com, iommu@lists.linux-foundation.org, sherry.hurwitz@amd.com, brijesh.singh@amd.com, leo.duran@amd.com, Thomas.Lendacky@amd.com Subject: [RFC v3 14/15] iommu/arm-smmu: do not advertise IOMMU_CAP_INTR_REMAP Date: Fri, 12 Feb 2016 08:13:16 +0000 Message-Id: <1455264797-2334-15-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455264797-2334-1-git-send-email-eric.auger@linaro.org> References: <1455264797-2334-1-git-send-email-eric.auger@linaro.org> Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu. Indeed the irq_remapping capability is abstracted on irqchip side for ARM as opposed to Intel IOMMU featuring IRQ remapping HW. So to check IRQ remmapping capability, the msi domain needs to be checked instead. Signed-off-by: Eric Auger --- drivers/iommu/arm-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index ae8a97d..9a83285 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1354,7 +1354,7 @@ static bool arm_smmu_capable(enum iommu_cap cap) */ return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + return false; /* MSIs are just memory writes */ case IOMMU_CAP_NOEXEC: return true; default: