diff mbox

[06/11] target-arm: Add comment about not implementing NSACR.RFR

Message ID 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show

Commit Message

Peter Maydell Feb. 15, 2016, 5:22 p.m. UTC 
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target-arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
1.9.1
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9998a25..37b5439 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5180,6 +5180,9 @@  static int bad_mode_switch(CPUARMState *env, int mode)
     case ARM_CPU_MODE_UND:
     case ARM_CPU_MODE_IRQ:
     case ARM_CPU_MODE_FIQ:
+        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
+         * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
+         */
         return 0;
     case ARM_CPU_MODE_MON:
         return !arm_is_secure(env);