From patchwork Thu Feb 18 13:46:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 62175 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp595115lbl; Thu, 18 Feb 2016 05:46:27 -0800 (PST) X-Received: by 10.98.74.202 with SMTP id c71mr10162190pfj.25.1455803187321; Thu, 18 Feb 2016 05:46:27 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id rd7si9547236pab.90.2016.02.18.05.46.27; Thu, 18 Feb 2016 05:46:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1426343AbcBRNq0 (ORCPT + 6 others); Thu, 18 Feb 2016 08:46:26 -0500 Received: from mail-lb0-f175.google.com ([209.85.217.175]:35269 "EHLO mail-lb0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1425322AbcBRNqZ (ORCPT ); Thu, 18 Feb 2016 08:46:25 -0500 Received: by mail-lb0-f175.google.com with SMTP id bc4so28602561lbc.2 for ; Thu, 18 Feb 2016 05:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=CX7+YWDuEApWzjjISQ2hBDQlsg/GnesdcXq0RAUr9Vs=; b=WZaxtlTOTr4rsbOyeWT8xftMg5nDyPrHe3/p01cSB+FrdOUpn5HVR62BqMr1sDkalL lLL0DRtcReqRdy6wHcnP0u+VQof8LBFCzCZ4WPpY/xcwkQKI0KbYcbUJZEOxHG8VwfSb HXyEymUXKDXj1U4/c3B/by5CYx2CR9IITiDSQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=CX7+YWDuEApWzjjISQ2hBDQlsg/GnesdcXq0RAUr9Vs=; b=U407fu43k5vnJ0rPacoyeK0OueZ8KuHjzDNZRmRddHlTIY1y7PW3D9iaT8l4ADgurz 49Dsfjs01HjjfdKl+bqeQiSK5XnNg6hPtRvrNnEkv5Ze4VbTu0r6/yrbPFEOxtD+MNdh /imHHdqc0pwn9gt8wq0SiyLdwqrfPZ8Y7udJqPtB5vOob82vEkEMwRpSHn8aJw4cbipI kYAO9BMT8ldXnnc6cVuDq7nC2llwLqhaghGyV9jedihr96eG0NE34Yjn4N5PkDOug0+Q 5TvKkykU2u7CzQU9+QonkmvutLzvA3wPPtNmtyqEOZDX1tNE9qr/C9M9YHIaw8xrpF/P Xcaw== X-Gm-Message-State: AG10YOSpdouUST9lJw2Hs0PVs7j3ChbUvqpNFHzqZEk3FJWUN/wZ+3zX6YaMrehv9yqgPGt9 X-Received: by 10.112.125.9 with SMTP id mm9mr2659836lbb.113.1455803183831; Thu, 18 Feb 2016 05:46:23 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id ke9sm950672lbc.28.2016.02.18.05.46.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Feb 2016 05:46:23 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Marc Zyngier Cc: Pawel Moll , Mark Rutland , Will Deacon , Rob Herring , Russell King , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 1/3] irqchip: gic/realview: support more RealView DCC variants Date: Thu, 18 Feb 2016 14:46:12 +0100 Message-Id: <1455803172-22747-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- This can be applied in isolation from the other patches so Marc one you're happy with it, please take it into the IRQchip tree. There are two compatible strings getting added to the device tree bindings so CC to the DT list. No biggie though, just figures out exactly what ARM custom GIC flavor it is. --- .../bindings/interrupt-controller/arm,gic.txt | 2 ++ drivers/irqchip/irq-gic-realview.c | 35 ++++++++++++++++++---- 2 files changed, 32 insertions(+), 5 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Arnd Bergmann Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 5a1cb4bc3dfe..0c80e6870645 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -16,6 +16,8 @@ Main node required properties: "arm,cortex-a15-gic" "arm,cortex-a7-gic" "arm,cortex-a9-gic" + "arm,eb11mp-gic" + "arm,eb11mp-revb-gic" "arm,gic-400" "arm,pl390" "arm,tc11mp-gic" diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c index aa46eb280a7f..224e83d5c056 100644 --- a/drivers/irqchip/irq-gic-realview.c +++ b/drivers/irqchip/irq-gic-realview.c @@ -10,7 +10,8 @@ #include #define REALVIEW_SYS_LOCK_OFFSET 0x20 -#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define REALVIEW_SYS_PLD_CTRL1 0x74 +#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8 #define VERSATILE_LOCK_VAL 0xA05F #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) #define PLD_INTMODE_LEGACY 0x0 @@ -18,26 +19,50 @@ #define PLD_INTMODE_NEW_NO_DCC BIT(23) #define PLD_INTMODE_FIQ_ENABLE BIT(24) +static const struct of_device_id syscon_pldset_of_match[] = { + { + .compatible = "arm,realview-eb-syscon", + }, + { + .compatible = "arm,realview-pb11mp-syscon", + }, + {}, +}; + static int __init realview_gic_of_init(struct device_node *node, struct device_node *parent) { static struct regmap *map; + struct device_node *np; + struct pld_setting *pldset; + u32 pld1_ctrl = REALVIEW_SYS_PLD_CTRL1; + + np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match, + (void *)&pldset); + if (!np) + return -ENODEV; + + /* For some reason RealView EB Rev B moved this register */ + if (of_device_is_compatible(np, "arm,eb11mp-revb-gic")) + pld1_ctrl = REALVIEW_EB_REVB_SYS_PLD_CTRL1; /* The PB11MPCore GIC needs to be configured in the syscon */ - map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + map = syscon_node_to_regmap(np); if (!IS_ERR(map)) { /* new irq mode with no DCC */ regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, VERSATILE_LOCK_VAL); - regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + regmap_update_bits(map, pld1_ctrl, PLD_INTMODE_NEW_NO_DCC, PLD_INTMODE_MASK); regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); - pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); } else { - pr_err("TC11MP GIC setup: could not find syscon\n"); + pr_err("RealView GIC setup: could not find syscon\n"); return -ENXIO; } return gic_of_init(node, parent); } IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_revb_gic, "arm,eb11mp-revb-gic", realview_gic_of_init);