| Message ID | 20221018-clk-range-checks-fixes-v2-56-f6736dec138e@cerno.tech |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: Make determine_rate mandatory for muxes | expand |
Hi Maxime, Le ven. 4 nov. 2022 à 14:18:13 +0100, Maxime Ripard <maxime@cerno.tech> a écrit : > The Ingenic CGU clocks implements a mux with a set_parent hook, but > doesn't provide a determine_rate implementation. > > This is a bit odd, since set_parent() is there to, as its name > implies, > change the parent of a clock. However, the most likely candidate to > trigger that parent change is a call to clk_set_rate(), with > determine_rate() figuring out which parent is the best suited for a > given rate. > > The other trigger would be a call to clk_set_parent(), but it's far > less > used, and it doesn't look like there's any obvious user for that > clock. > > So, the set_parent hook is effectively unused, possibly because of an > oversight. However, it could also be an explicit decision by the > original author to avoid any reparenting but through an explicit call > to > clk_set_parent(). > > The driver does implement round_rate() though, which means that we can > change the rate of the clock, but we will never get to change the > parent. > > However, It's hard to tell whether it's been done on purpose or not. > > Since we'll start mandating a determine_rate() implementation, let's > convert the round_rate() implementation to a determine_rate(), which > will also make the current behavior explicit. And if it was an > oversight, the clock behaviour can be adjusted later on. So it's partly on purpose, partly because I didn't know about .determine_rate. There's nothing odd about having a lonely .set_parent callback; in my case the clocks are parented from the device tree. Having the clocks driver trigger a parent change when requesting a rate change sounds very dangerous, IMHO. My MMC controller can be parented to the external 48 MHz oscillator, and if the card requests 50 MHz, it could switch to one of the PLLs. That works as long as the PLLs don't change rate, but if one is configured as driving the CPU clock, it becomes messy. The thing is, the clocks driver has no way to know whether or not it is "safe" to use a designated parent. For that reason, in practice, I never actually want to have a clock re-parented - it's almost always a bad idea vs. sticking to the parent clock configured in the DTS. > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > --- > drivers/clk/ingenic/cgu.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c > index 1f7ba30f5a1b..0c9c8344ad11 100644 > --- a/drivers/clk/ingenic/cgu.c > +++ b/drivers/clk/ingenic/cgu.c > @@ -491,22 +491,23 @@ ingenic_clk_calc_div(struct clk_hw *hw, > return div; > } > > -static long > -ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, > - unsigned long *parent_rate) > +static int ingenic_clk_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > { > struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); > const struct ingenic_cgu_clk_info *clk_info = > to_clk_info(ingenic_clk); > unsigned int div = 1; > > if (clk_info->type & CGU_CLK_DIV) > - div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); > + div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate, > + req->rate); Sorry but I'm not sure that this works. You replace the "parent_rate" with the "best_parent_rate", and that means you only check the requested rate vs. the parent with the highest frequency, and not vs. the actual parent that will be used. Cheers, -Paul > else if (clk_info->type & CGU_CLK_FIXDIV) > div = clk_info->fixdiv.div; > else if (clk_hw_can_set_rate_parent(hw)) > - *parent_rate = req_rate; > + req->best_parent_rate = req->rate; > > - return DIV_ROUND_UP(*parent_rate, div); > + req->rate = DIV_ROUND_UP(req->best_parent_rate, div); > + return 0; > } > > static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu, > @@ -626,7 +627,7 @@ static const struct clk_ops ingenic_clk_ops = { > .set_parent = ingenic_clk_set_parent, > > .recalc_rate = ingenic_clk_recalc_rate, > - .round_rate = ingenic_clk_round_rate, > + .determine_rate = ingenic_clk_determine_rate, > .set_rate = ingenic_clk_set_rate, > > .enable = ingenic_clk_enable, > > -- > b4 0.11.0-dev-99e3a
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 1f7ba30f5a1b..0c9c8344ad11 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -491,22 +491,23 @@ ingenic_clk_calc_div(struct clk_hw *hw, return div; } -static long -ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, - unsigned long *parent_rate) +static int ingenic_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); unsigned int div = 1; if (clk_info->type & CGU_CLK_DIV) - div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); + div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate, + req->rate); else if (clk_info->type & CGU_CLK_FIXDIV) div = clk_info->fixdiv.div; else if (clk_hw_can_set_rate_parent(hw)) - *parent_rate = req_rate; + req->best_parent_rate = req->rate; - return DIV_ROUND_UP(*parent_rate, div); + req->rate = DIV_ROUND_UP(req->best_parent_rate, div); + return 0; } static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu, @@ -626,7 +627,7 @@ static const struct clk_ops ingenic_clk_ops = { .set_parent = ingenic_clk_set_parent, .recalc_rate = ingenic_clk_recalc_rate, - .round_rate = ingenic_clk_round_rate, + .determine_rate = ingenic_clk_determine_rate, .set_rate = ingenic_clk_set_rate, .enable = ingenic_clk_enable,
The Ingenic CGU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/clk/ingenic/cgu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)