ARM: realview: DT support for the PBA8

Message ID 1456303714-31039-1-git-send-email-linus.walleij@linaro.org
State New
Headers show

Commit Message

Linus Walleij Feb. 24, 2016, 8:48 a.m.
This adds a devicetree for the ARM RealView PBA8 platform,
also known as HBI-0178, "RealView(R) Platform Baseboard for
Cortex(TM)-A8".

Tested in QEMU with -M realview-pb-a8 and works like a charm,
however with these annoying boot messages:

of_amba_device_create(): amba_device_add()
    failed (-19) for /soc/sysctl@10001000
of_amba_device_create(): amba_device_add()
    failed (-19) for /soc/ssp@1000d000
of_amba_device_create(): amba_device_add()
    failed (-19) for /soc/timer@10018000
of_amba_device_create(): amba_device_add()
    failed (-19) for /soc/timer@10019000
of_amba_device_create(): amba_device_add()
    failed (-19) for /soc/sysctl@1001a000

I think this is because these PrimeCells do not exist in the
QEMU machine model but would work fine on the real hardware.
QEMU still works, because the SP810 clocks will anyway probe,
as they are not amba_devices but use the special CLK_OF_DECLARE()
probing macro.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

---
 arch/arm/boot/dts/Makefile              |   3 +-
 arch/arm/boot/dts/arm-realview-pba8.dts | 620 ++++++++++++++++++++++++++++++++
 2 files changed, 622 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/arm-realview-pba8.dts

-- 
2.4.3


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Comments

Arnd Bergmann Feb. 24, 2016, 8:53 a.m. | #1
On Wednesday 24 February 2016 09:48:34 Linus Walleij wrote:
> This adds a devicetree for the ARM RealView PBA8 platform,

> also known as HBI-0178, "RealView(R) Platform Baseboard for

> Cortex(TM)-A8".


Nice!

> Tested in QEMU with -M realview-pb-a8 and works like a charm,

> however with these annoying boot messages:

> 

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/sysctl@10001000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/ssp@1000d000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/timer@10018000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/timer@10019000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/sysctl@1001a000

> 

> I think this is because these PrimeCells do not exist in the

> QEMU machine model but would work fine on the real hardware.

> QEMU still works, because the SP810 clocks will anyway probe,

> as they are not amba_devices but use the special CLK_OF_DECLARE()

> probing macro.

> 


I think we can treat this as a harmless qemu deficiency.

It would be nice to fix qemu to avoid the warnings, but as you say
it's not a showstopper.

	Arnd

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Peter Maydell Feb. 24, 2016, 10:18 a.m. | #2
On 24 February 2016 at 08:48, Linus Walleij <linus.walleij@linaro.org> wrote:
> This adds a devicetree for the ARM RealView PBA8 platform,

> also known as HBI-0178, "RealView(R) Platform Baseboard for

> Cortex(TM)-A8".

>

> Tested in QEMU with -M realview-pb-a8 and works like a charm,

> however with these annoying boot messages:

>

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/sysctl@10001000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/ssp@1000d000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/timer@10018000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/timer@10019000

> of_amba_device_create(): amba_device_add()

>     failed (-19) for /soc/sysctl@1001a000


The missing timers would be a two-line QEMU patch,
as would the ssp, since we have SP804 and PL022 device
models. We have no model of the SP810 but it would probably
not be too hard to write a "mostly does nothing" version.
Patches welcome :-)

thanks
-- PMM

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Robin Murphy Feb. 24, 2016, 12:24 p.m. | #3
Hi Linus,

On 24/02/16 08:48, Linus Walleij wrote:
> This adds a devicetree for the ARM RealView PBA8 platform,

> also known as HBI-0178, "RealView(R) Platform Baseboard for

> Cortex(TM)-A8".

>

> Tested in QEMU with -M realview-pb-a8 and works like a charm,

> however with these annoying boot messages:

>

> of_amba_device_create(): amba_device_add()

>      failed (-19) for /soc/sysctl@10001000

> of_amba_device_create(): amba_device_add()

>      failed (-19) for /soc/ssp@1000d000

> of_amba_device_create(): amba_device_add()

>      failed (-19) for /soc/timer@10018000

> of_amba_device_create(): amba_device_add()

>      failed (-19) for /soc/timer@10019000

> of_amba_device_create(): amba_device_add()

>      failed (-19) for /soc/sysctl@1001a000

>

> I think this is because these PrimeCells do not exist in the

> QEMU machine model but would work fine on the real hardware.

> QEMU still works, because the SP810 clocks will anyway probe,

> as they are not amba_devices but use the special CLK_OF_DECLARE()

> probing macro.


And here I thought that big black box on the far corner of my desk was 
only good for taking up space. I have no idea of its provenance, but 
here's what it had to say (using appended dtb and a hack in the 
decompressor to set r1=-1, r2=0 because I can't be bothered faffing with 
a 2010-vintage u-boot):

RealView PBA8 #go 0x7fc0
## Starting application at 0x00007FC0 ...
Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 4.5.0-rc4-00004-ga81bbd8-dirty (robmur01@e104324-lin) (gcc 
version 5.2.1 20151005 (Linaro GCC 5.2-2015.11-2) ) #16 SMP Wed Feb 24 
11:39:06 GMT 2016
CPU: ARMv7 Processor [411fc081] revision 1 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: ARM RealView PB-A8
bootconsole [earlycon0] enabled
Memory policy: Data cache writeback
CPU: All CPU(s) started in SVC mode.
PERCPU: Embedded 11 pages/cpu @c7ee4000 s13376 r8192 d23488 u45056
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: root=/dev/mmcblk0p1 rw rootwait console=ttyAMA0 
earlyprintk
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 124392K/131072K available (3863K kernel code, 128K rwdata, 1076K 
rodata, 212K init, 138K bss, 6680K reserved, 0K cma-reserved)
Virtual kernel memory layout:
     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
     DTCM    : 0xfffe8000 - 0xfffe8000   (   0 kB)
     ITCM    : 0xfffe0000 - 0xfffe0000   (   0 kB)
     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
     vmalloc : 0xc8800000 - 0xff800000   ( 880 MB)
     lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
     modules : 0xbf000000 - 0xc0000000   (  16 MB)
       .text : 0xc0008000 - 0xc04dafec   (4940 kB)
       .init : 0xc04db000 - 0xc0510000   ( 212 kB)
       .data : 0xc0510000 - 0xc05303a0   ( 129 kB)
        .bss : 0xc0531000 - 0xc05538e0   ( 139 kB)
Hierarchical RCU implementation.
	Build-time adjustment of leaf fanout to 32.
	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
NR_IRQS:16 nr_irqs:16 16
L2C: failed to init: -19
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at drivers/clk/versatile/clk-sp810.c:137 
clk_sp810_of_setup+0x124/0x168()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.5.0-rc4-00004-ga81bbd8-dirty #16
Hardware name: ARM RealView Machine (Device Tree Support)
Backtrace:
[<c0013a98>] (dump_backtrace) from [<c0013c8c>] (show_stack+0x18/0x1c)
  r6:600000d3 r5:00000000 r4:c051f800
[<c0013c74>] (show_stack) from [<c01b26b0>] (dump_stack+0x94/0xb0)
[<c01b261c>] (dump_stack) from [<c0025884>] (warn_slowpath_common+0x7c/0xb8)
  r6:00000009 r5:00000089 r4:00000000
[<c0025808>] (warn_slowpath_common) from [<c0025964>] 
(warn_slowpath_null+0x24/0x28)
  r8:c7ef7570 r7:00000001 r6:c7ef7394 r5:c7807980 r4:c780798c
[<c0025940>] (warn_slowpath_null) from [<c04f4f34>] 
(clk_sp810_of_setup+0x124/0x168)
[<c04f4e10>] (clk_sp810_of_setup) from [<c04f4714>] 
(of_clk_init+0x13c/0x1e0)
  r10:00000003 r9:00000001 r8:00000000 r7:00000001 r6:c0511f6c r5:c78054c0
  r4:c0511f74
[<c04f45d8>] (of_clk_init) from [<c04ddac0>] (time_init+0x2c/0x38)
  r10:c05008c0 r9:c7ffc840 r8:c0531000 r7:c05127c0 r6:c0531000 r5:ffffffff
  r4:00000000
[<c04dda94>] (time_init) from [<c04dbbc4>] (start_kernel+0x248/0x364)
[<c04db97c>] (start_kernel) from [<0000807c>] (0x807c)
  r10:00000000 r9:411fc081 r8:00004059 r7:c0516910 r6:c05008bc r5:c051286c
  r4:c0531294
---[ end trace cb88537fdc8fa200 ]---
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at drivers/clk/versatile/clk-sp810.c:137 
clk_sp810_of_setup+0x124/0x168()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 
4.5.0-rc4-00004-ga81bbd8-dirty #16
Hardware name: ARM RealView Machine (Device Tree Support)
Backtrace:
[<c0013a98>] (dump_backtrace) from [<c0013c8c>] (show_stack+0x18/0x1c)
  r6:600000d3 r5:00000000 r4:c051f800
[<c0013c74>] (show_stack) from [<c01b26b0>] (dump_stack+0x94/0xb0)
[<c01b261c>] (dump_stack) from [<c0025884>] (warn_slowpath_common+0x7c/0xb8)
  r6:00000009 r5:00000089 r4:00000000
[<c0025808>] (warn_slowpath_common) from [<c0025964>] 
(warn_slowpath_null+0x24/0x28)
  r8:c7ef7570 r7:00000002 r6:c7ef7394 r5:c7807980 r4:c78079a4
[<c0025940>] (warn_slowpath_null) from [<c04f4f34>] 
(clk_sp810_of_setup+0x124/0x168)
[<c04f4e10>] (clk_sp810_of_setup) from [<c04f4714>] 
(of_clk_init+0x13c/0x1e0)
  r10:00000003 r9:00000001 r8:00000000 r7:00000001 r6:c0511f6c r5:c78054c0
  r4:c0511f74
[<c04f45d8>] (of_clk_init) from [<c04ddac0>] (time_init+0x2c/0x38)
  r10:c05008c0 r9:c7ffc840 r8:c0531000 r7:c05127c0 r6:c0531000 r5:ffffffff
  r4:00000000
[<c04dda94>] (time_init) from [<c04dbbc4>] (start_kernel+0x248/0x364)
[<c04db97c>] (start_kernel) from [<0000807c>] (0x807c)
  r10:00000000 r9:411fc081 r8:00004059 r7:c0516910 r6:c05008bc r5:c051286c
  r4:c0531294
---[ end trace cb88537fdc8fa201 ]---
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at drivers/clk/versatile/clk-sp810.c:137 
clk_sp810_of_setup+0x124/0x168()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 
4.5.0-rc4-00004-ga81bbd8-dirty #16
Hardware name: ARM RealView Machine (Device Tree Support)
Backtrace:
[<c0013a98>] (dump_backtrace) from [<c0013c8c>] (show_stack+0x18/0x1c)
  r6:600000d3 r5:00000000 r4:c051f800
[<c0013c74>] (show_stack) from [<c01b26b0>] (dump_stack+0x94/0xb0)
[<c01b261c>] (dump_stack) from [<c0025884>] (warn_slowpath_common+0x7c/0xb8)
  r6:00000009 r5:00000089 r4:00000000
[<c0025808>] (warn_slowpath_common) from [<c0025964>] 
(warn_slowpath_null+0x24/0x28)
  r8:c7ef7570 r7:00000003 r6:c7ef7394 r5:c7807980 r4:c78079bc
[<c0025940>] (warn_slowpath_null) from [<c04f4f34>] 
(clk_sp810_of_setup+0x124/0x168)
[<c04f4e10>] (clk_sp810_of_setup) from [<c04f4714>] 
(of_clk_init+0x13c/0x1e0)
  r10:00000003 r9:00000001 r8:00000000 r7:00000001 r6:c0511f6c r5:c78054c0
  r4:c0511f74
[<c04f45d8>] (of_clk_init) from [<c04ddac0>] (time_init+0x2c/0x38)
  r10:c05008c0 r9:c7ffc840 r8:c0531000 r7:c05127c0 r6:c0531000 r5:ffffffff
  r4:00000000
[<c04dda94>] (time_init) from [<c04dbbc4>] (start_kernel+0x248/0x364)
[<c04db97c>] (start_kernel) from [<0000807c>] (0x807c)
  r10:00000000 r9:411fc081 r8:00004059 r7:c0516910 r6:c05008bc r5:c051286c
  r4:c0531294
---[ end trace cb88537fdc8fa202 ]---
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at drivers/clk/versatile/clk-sp810.c:137 
clk_sp810_of_setup+0x124/0x168()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 
4.5.0-rc4-00004-ga81bbd8-dirty #16
Hardware name: ARM RealView Machine (Device Tree Support)
Backtrace:
[<c0013a98>] (dump_backtrace) from [<c0013c8c>] (show_stack+0x18/0x1c)
  r6:600000d3 r5:00000000 r4:c051f800
[<c0013c74>] (show_stack) from [<c01b26b0>] (dump_stack+0x94/0xb0)
[<c01b261c>] (dump_stack) from [<c0025884>] (warn_slowpath_common+0x7c/0xb8)
  r6:00000009 r5:00000089 r4:00000000
[<c0025808>] (warn_slowpath_common) from [<c0025964>] 
(warn_slowpath_null+0x24/0x28)
  r8:c7ef7570 r7:00000004 r6:c7ef7394 r5:c7807980 r4:c78079d4
[<c0025940>] (warn_slowpath_null) from [<c04f4f34>] 
(clk_sp810_of_setup+0x124/0x168)
[<c04f4e10>] (clk_sp810_of_setup) from [<c04f4714>] 
(of_clk_init+0x13c/0x1e0)
  r10:00000003 r9:00000001 r8:00000000 r7:00000001 r6:c0511f6c r5:c78054c0
  r4:c0511f74
[<c04f45d8>] (of_clk_init) from [<c04ddac0>] (time_init+0x2c/0x38)
  r10:c05008c0 r9:c7ffc840 r8:c0531000 r7:c05127c0 r6:c0531000 r5:ffffffff
  r4:00000000
[<c04dda94>] (time_init) from [<c04dbbc4>] (start_kernel+0x248/0x364)
[<c04db97c>] (start_kernel) from [<0000807c>] (0x807c)
  r10:00000000 r9:411fc081 r8:00004059 r7:c0516910 r6:c05008bc r5:c051286c
  r4:c0531294
---[ end trace cb88537fdc8fa203 ]---
clk: couldn't get parent clock 0 for /soc/sysctl@1001a000
clk: couldn't get parent clock 0 for /soc/sysctl@1001a000
clocksource: arm,sp804: mask: 0xffffffff max_cycles: 0xffffffff, 
max_idle_ns: 1911260446275 ns
sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 
2147483647500ns
Console: colour dummy device 80x30
Calibrating delay loop... 743.83 BogoMIPS (lpj=3719168)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket -1, mpidr 0
Setting up static identity map for 0x82a0 - 0x8310
Brought up 1 CPUs
SMP: Total of 1 processors activated (743.83 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, 
max_idle_ns: 19112604462750000 ns
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
hw-breakpoint: debug architecture 0x4 unsupported.
Serial: AMBA PL011 UART driver
10009000.serial: ttyAMA0 at MMIO 0x10009000 (irq = 20, base_baud = 0) is 
a PL011 rev2
console [ttyAMA0] enabled
console [ttyAMA0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
1000a000.serial: ttyAMA1 at MMIO 0x1000a000 (irq = 21, base_baud = 0) is 
a PL011 rev2
1000b000.serial: ttyAMA2 at MMIO 0x1000b000 (irq = 22, base_baud = 0) is 
a PL011 rev2
1000c000.serial: ttyAMA3 at MMIO 0x1000c000 (irq = 36, base_baud = 0) is 
a PL011 rev2
ssp-pl022 1000d000.ssp: ARM PL022 driver, device ID: 0x00041022
ssp-pl022 1000d000.ssp: mapped registers from 0x1000d000 to c8884000
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
i2c i2c-0: Failed to register i2c client ds1338 at 0x68 (-16)
i2c i2c-0: Can't create device at 0x68
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm,sp804
NET: Registered protocol family 2
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 1024 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
futex hash table entries: 256 (order: 2, 16384 bytes)
io scheduler noop registered
io scheduler deadline registered (default)
pl061_gpio 10013000.gpio: PL061 GPIO chip @0x10013000 registered
pl061_gpio 10014000.gpio: PL061 GPIO chip @0x10014000 registered
pl061_gpio 10015000.gpio: PL061 GPIO chip @0x10015000 registered
clcd-pl11x 10020000.clcd: PL111 rev0 at 0x10020000
clcd-pl11x 10020000.clcd: /issp/clcd@10020000 hardware, 640x480@59 display
Console: switching to colour frame buffer device 80x30
realview-soc soc: RealView Syscon Core ID: 0x2178f505, HBI-178
libphy: smsc911x-mdio: probed
SMSC LAN911x Internal PHY 4e000000.etherne:01: attached PHY driver [SMSC 
LAN911x Internal PHY] (mii_bus:phy_addr=4e000000.etherne:01, irq=-1)
smsc911x 4e000000.ethernet eth0: MAC Address: 00:02:f7:00:0a:c2
isp1760 4f000000.usb: bus width: 32, oc: digital
isp1760 4f000000.usb: NXP ISP1760 USB Host Controller
isp1760 4f000000.usb: new USB bus registered, assigned bus number 1
isp1760 4f000000.usb: irq 19, io mem 0x4f000000
isp1760 4f000000.usb: USB ISP 1761 HW rev. 1 started
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
ISP1760 USB device initialised
mousedev: PS/2 mouse device common for all mice
rtc-ds1307 0-0068: rtc core: registered ds1338 as rtc0
rtc-ds1307 0-0068: 56 bytes nvram
rtc-pl031 10017000.rtc: rtc core: registered pl031 as rtc1
versatile reboot driver registered
mmci-pl18x 10005000.mmcsd: Got CD GPIO
mmci-pl18x 10005000.mmcsd: Got WP GPIO
mmci-pl18x 10005000.mmcsd: mmc0: PL180 manf 41 rev0 at 0x10005000 irq 
32,33 (pio)
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
aaci-pl041 10004000.aaci: ARM AC'97 Interface PL041 rev0 at 0x10004000, 
irq 31
aaci-pl041 10004000.aaci: FIFO 512 entries
NET: Registered protocol family 17
Registering SWP/SWPB emulation handler
isp1760 4f000000.usb: port 1 high speed
rtc-ds1307 0-0068: setting system clock to 2000-01-01 00:17:12 UTC 
(946685832)
ALSA device list:
   #0: ARM AC'97 Interface PL041 rev0 at 0x10004000, irq 31
usb 1-1: new high-speed USB device number 2 using isp1760
isp1760 4f000000.usb: port 1 high speed
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 3 ports detected
atkbd serio0: keyboard reset failed on 10006000.kmi
atkbd serio1: keyboard reset failed on 10007000.kmi
atkbd serio0: keyboard reset failed on 10006000.kmi
atkbd serio1: keyboard reset failed on 10007000.kmi
Waiting for root device /dev/mmcblk0p1...


It then fails to notice my SD card, even if I eject and reinsert it :(

Robin.

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Robin Murphy Feb. 24, 2016, 3:48 p.m. | #4
On 24/02/16 12:24, Robin Murphy wrote:
> Hi Linus,

>

> On 24/02/16 08:48, Linus Walleij wrote:

>> This adds a devicetree for the ARM RealView PBA8 platform,

>> also known as HBI-0178, "RealView(R) Platform Baseboard for

>> Cortex(TM)-A8".

>>

>> Tested in QEMU with -M realview-pb-a8 and works like a charm,

>> however with these annoying boot messages:

>>

>> of_amba_device_create(): amba_device_add()

>>      failed (-19) for /soc/sysctl@10001000

>> of_amba_device_create(): amba_device_add()

>>      failed (-19) for /soc/ssp@1000d000

>> of_amba_device_create(): amba_device_add()

>>      failed (-19) for /soc/timer@10018000

>> of_amba_device_create(): amba_device_add()

>>      failed (-19) for /soc/timer@10019000

>> of_amba_device_create(): amba_device_add()

>>      failed (-19) for /soc/sysctl@1001a000

>>

>> I think this is because these PrimeCells do not exist in the

>> QEMU machine model but would work fine on the real hardware.

>> QEMU still works, because the SP810 clocks will anyway probe,

>> as they are not amba_devices but use the special CLK_OF_DECLARE()

>> probing macro.

>

> And here I thought that big black box on the far corner of my desk was

> only good for taking up space. I have no idea of its provenance, but

> here's what it had to say (using appended dtb and a hack in the

> decompressor to set r1=-1, r2=0 because I can't be bothered faffing with

> a 2010-vintage u-boot):

>

> RealView PBA8 #go 0x7fc0

> ## Starting application at 0x00007FC0 ...

> Uncompressing Linux... done, booting the kernel.

> Booting Linux on physical CPU 0x0


[...]

> pl061_gpio 10013000.gpio: PL061 GPIO chip @0x10013000 registered

> pl061_gpio 10014000.gpio: PL061 GPIO chip @0x10014000 registered

> pl061_gpio 10015000.gpio: PL061 GPIO chip @0x10015000 registered


[...]

> mmci-pl18x 10005000.mmcsd: Got CD GPIO

> mmci-pl18x 10005000.mmcsd: Got WP GPIO


[...]

> Waiting for root device /dev/mmcblk0p1...

>

>

> It then fails to notice my SD card, even if I eject and reinsert it :(


Ah, it's because it's requesting those GPIOS from &gpio1, rather than 
&gpio2 where they really are. With that fixed up the card detect now 
works, but apparently nothing I have around my desk actually supports 
3.3V...

Robin.


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Linus Walleij Feb. 24, 2016, 3:52 p.m. | #5
On Wed, Feb 24, 2016 at 1:24 PM, Robin Murphy <robin.murphy@arm.com> wrote:

> And here I thought that big black box on the far corner of my desk was only

> good for taking up space. I have no idea of its provenance, but here's what

> it had to say (using appended dtb and a hack in the decompressor to set

> r1=-1, r2=0 because I can't be bothered faffing with a 2010-vintage u-boot):


Nice! Thanks!

> ------------[ cut here ]------------

> WARNING: CPU: 0 PID: 0 at drivers/clk/versatile/clk-sp810.c:137


This noise is fixed in another separate patch I sent earlier:
http://permalink.gmane.org/gmane.linux.kernel.clk/4383

> Waiting for root device /dev/mmcblk0p1...

>

> It then fails to notice my SD card, even if I eject and reinsert it :(


Fixing a v2 as we speak.

Yours,
Linus Walleij

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Linus Walleij Feb. 24, 2016, 3:59 p.m. | #6
On Wed, Feb 24, 2016 at 4:52 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Wed, Feb 24, 2016 at 1:24 PM, Robin Murphy <robin.murphy@arm.com> wrote:


>> Waiting for root device /dev/mmcblk0p1...

>>

>> It then fails to notice my SD card, even if I eject and reinsert it :(

>

> Fixing a v2 as we speak.


Also notice: if you want working graphics, I have a pending CLCD patch
set for that, and then there is a patch for reset too. I still hope to land
it all for v4.6 and delete the board files but it depends on a few subsystem
maintainers.

Yours,
Linus Walleij

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Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 39deb1741465..bf01d0641531 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -537,7 +537,8 @@  dtb-$(CONFIG_ARCH_REALVIEW) += \
 	arm-realview-eb.dtb \
 	arm-realview-eb-11mp.dtb \
 	arm-realview-eb-11mp-revb.dtb \
-	arm-realview-eb-a9mp.dtb
+	arm-realview-eb-a9mp.dtb \
+	arm-realview-pba8.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3036-evb.dtb \
 	rk3036-kylin.dtb \
diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts
new file mode 100644
index 000000000000..722b29308720
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-pba8.dts
@@ -0,0 +1,620 @@ 
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+	model = "ARM RealView PB-A8";
+	compatible = "arm,realview-pba8";
+	arm,hbi = <0x178>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c;
+	};
+
+	memory {
+		/* 128 MiB memory @ 0x0 */
+		reg = <0x00000000 0x08000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "arm,realview-smp";
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0>;
+		};
+	};
+
+	pmu: pmu@0 {
+		compatible = "arm,cortex-a8-pmu";
+		interrupt-parent = <&intc>;
+		interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	/* The voltage to the MMC card is hardwired at 3.3V */
+	vmmc: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+        };
+
+	veth: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "veth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+	};
+
+	xtal24mhz: xtal24mhz@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+
+	refclk32khz: refclk32khz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	timclk: timclk@1M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <24>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	mclk: mclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	kmiclk: kmiclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	sspclk: sspclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	uartclk: uartclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	wdogclk: wdogclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	/* FIXME: this actually hangs off the PLL clocks */
+	pclk: pclk@0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	flash0@40000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x40000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	flash1@44000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x44000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	/* SMSC 9118 ethernet with PHY and EEPROM */
+	ethernet: ethernet@4e000000 {
+		compatible = "smsc,lan9118", "smsc,lan9115";
+		reg = <0x4e000000 0x10000>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+		vdd33a-supply = <&veth>;
+		vddvario-supply = <&veth>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	usb: usb@4f000000 {
+		compatible = "nxp,usb-isp1761";
+		reg = <0x4f000000 0x20000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+		port1-otg;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,realview-pba8-soc", "simple-bus";
+		regmap = <&syscon>;
+		ranges;
+
+		syscon: syscon@10000000 {
+			compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd";
+			reg = <0x10000000 0x1000>;
+
+			led@08.0 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x01>;
+				label = "versatile:0";
+				linux,default-trigger = "heartbeat";
+				default-state = "on";
+			};
+			led@08.1 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x02>;
+				label = "versatile:1";
+				linux,default-trigger = "mmc0";
+				default-state = "off";
+			};
+			led@08.2 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x04>;
+				label = "versatile:2";
+				linux,default-trigger = "cpu0";
+				default-state = "off";
+			};
+			led@08.3 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x08>;
+				label = "versatile:3";
+				default-state = "off";
+			};
+			led@08.4 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x10>;
+				label = "versatile:4";
+				default-state = "off";
+			};
+			led@08.5 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x20>;
+				label = "versatile:5";
+				default-state = "off";
+			};
+			led@08.6 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x40>;
+				label = "versatile:6";
+				default-state = "off";
+			};
+			led@08.7 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x80>;
+				label = "versatile:7";
+				default-state = "off";
+			};
+			oscclk0: osc0@0c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x0C>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk1: osc1@10 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x10>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk2: osc2@14 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x14>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk3: osc3@18 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x18>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk4: osc4@1c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x1c>;
+				clocks = <&xtal24mhz>;
+			};
+		};
+
+		sp810_syscon0: sysctl@10001000 {
+			compatible = "arm,sp810", "arm,primecell";
+			reg = <0x10001000 0x1000>;
+			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
+			clock-names = "refclk", "timclk", "apb_pclk";
+			#clock-cells = <1>;
+			clock-output-names = "timerclk0",
+					     "timerclk1",
+					     "timerclk2",
+					     "timerclk3";
+			assigned-clocks = <&sp810_syscon0 0>,
+					  <&sp810_syscon0 1>,
+					  <&sp810_syscon0 2>,
+					  <&sp810_syscon0 3>;
+			assigned-clock-parents = <&timclk>,
+					       <&timclk>,
+					       <&timclk>,
+					       <&timclk>;
+		};
+
+		i2c: i2c@10002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "arm,versatile-i2c";
+			reg = <0x10002000 0x1000>;
+
+			rtc@68 {
+				compatible = "dallas,ds1338";
+				reg = <0x68>;
+			};
+		};
+
+		serial0: serial@10009000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x10009000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		serial1: serial@1000a000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000a000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		serial2: serial@1000b000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000b000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		ssp: ssp@1000d000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x1000d000 0x1000>;
+			clocks = <&sspclk>, <&pclk>;
+			clock-names = "SSPCLK", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wdog0: watchdog@1000f000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x1000f000 0x1000>;
+			clocks = <&wdogclk>, <&pclk>;
+			clock-names = "wdogclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		wdog1: watchdog@10010000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x10010000 0x1000>;
+			clocks = <&wdogclk>, <&pclk>;
+			clock-names = "wdogclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer01: timer@10011000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10011000 0x1000>;
+			clocks = <&sp810_syscon0 0>,
+			         <&sp810_syscon0 1>,
+				 <&pclk>;
+			clock-names = "timerclk0",
+				    "timerclk1",
+				    "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer23: timer@10012000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10012000 0x1000>;
+			clocks = <&sp810_syscon0 2>,
+			         <&sp810_syscon0 3>,
+				 <&pclk>;
+			clock-names = "timerclk2",
+				    "timerclk3",
+				    "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+			arm,sp804-has-irq = <1>;
+		};
+
+		gpio0: gpio@10013000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10013000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gpio1: gpio@10014000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10014000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gpio2: gpio@10015000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10015000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		/* DVI serial bus control is at 10016000 */
+
+		rtc: rtc@10017000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x10017000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer45: timer@10018000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10018000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timerclk4", "timerclk5", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer67: timer@10019000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10019000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timerclk6", "timerclk7", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sp810_syscon1: sysctl@1001a000 {
+			compatible = "arm,sp810", "arm,primecell";
+			reg = <0x1001a000 0x1000>;
+			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
+			clock-names = "refclk", "timclk", "apb_pclk";
+			#clock-cells = <1>;
+			clock-output-names = "timerclk4",
+					     "timerclk5",
+					     "timerclk6",
+					     "timerclk7";
+			assigned-clocks = <&sp810_syscon1 0>,
+					  <&sp810_syscon1 1>,
+					  <&sp810_syscon1 2>,
+					  <&sp810_syscon1 3>;
+			assigned-clock-parents = <&timclk>,
+					       <&timclk>,
+					       <&timclk>,
+					       <&timclk>;
+		};
+
+		/* Primary GIC PL390 interrupt controller in the test chip */
+		intc: interrupt-controller@1e000000 {
+			compatible = "arm,pl390";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0x1e001000 0x1000>,
+			      <0x1e000000 0x100>;
+		};
+	};
+
+
+	/* These peripherals are inside the FPGA */
+	fpga {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		aaci: aaci@10004000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x10004000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		mmc: mmcsd@10005000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x10005000 0x1000>;
+
+			/* Due to frequent FIFO overruns, use just 500 kHz */
+			max-frequency = <500000>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			clocks = <&mclk>, <&pclk>;
+			clock-names = "mclk", "apb_pclk";
+			vmmc-supply = <&vmmc>;
+			cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+			wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 18 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		kmi0: kmi@10006000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10006000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		kmi1: kmi@10007000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10007000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		serial3: serial@1000c000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000c000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+			interrupt-parent = <&intc>;
+			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	/* These peripherals are inside the NEC ISSP */
+	issp {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		clcd: clcd@10020000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0x10020000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "combined";
+			clocks = <&oscclk4>, <&pclk>;
+			clock-names = "clcdclk", "apb_pclk";
+
+			port {
+				clcd_pads: endpoint {
+					remote-endpoint = <&clcd_panel>;
+					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+				};
+			};
+
+			panel {
+				compatible = "panel-dpi";
+
+				port {
+					clcd_panel: endpoint {
+						remote-endpoint = <&clcd_pads>;
+					};
+				};
+
+				/* Standard 640x480 VGA timings */
+				panel-timing {
+					clock-frequency = <25175000>;
+					hactive = <640>;
+					hback-porch = <48>;
+					hfront-porch = <16>;
+					hsync-len = <96>;
+					vactive = <480>;
+					vback-porch = <33>;
+					vfront-porch = <10>;
+					vsync-len = <2>;
+				};
+			};
+		};
+	};
+};
+