| Message ID | 20221122133551.91536-1-nathan.morrison@timesys.com |
|---|---|
| State | New |
| Headers | show |
| Series | spi: cadence-quadspi: Properly pass buswidth through to underlying SPI subsystem via buswidth_override_bits instead of mode_bits. | expand |
Please disregard. This isn't quite right. I'll resubmit a better patch On 11/22/22 08:35, Nathan Barrett-Morrison wrote: > While trying to enable Octal SPI mode, it was observed that > SPI_RX_OCTAL/SPI_TX_OCTAL were not propagating into the spi_device > spi->mode setting. This was causing the SPI device to always > operate in 1x mode instead of the desired 8x mode. > > Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> > --- > drivers/spi/spi-cadence-quadspi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c > index 447230547945..c92a95bdaa05 100644 > --- a/drivers/spi/spi-cadence-quadspi.c > +++ b/drivers/spi/spi-cadence-quadspi.c > @@ -1589,7 +1589,7 @@ static int cqspi_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "spi_alloc_master failed\n"); > return -ENOMEM; > } > - master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; > + master->buswidth_override_bits = SPI_RX_QUAD | SPI_RX_DUAL; > master->mem_ops = &cqspi_mem_ops; > master->mem_caps = &cqspi_mem_caps; > master->dev.of_node = pdev->dev.of_node; > @@ -1686,7 +1686,7 @@ static int cqspi_probe(struct platform_device *pdev) > cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, > cqspi->master_ref_clk_hz); > if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) > - master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; > + master->buswidth_override_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; > if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) > cqspi->use_direct_mode = true; > if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 447230547945..c92a95bdaa05 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1589,7 +1589,7 @@ static int cqspi_probe(struct platform_device *pdev) dev_err(&pdev->dev, "spi_alloc_master failed\n"); return -ENOMEM; } - master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; + master->buswidth_override_bits = SPI_RX_QUAD | SPI_RX_DUAL; master->mem_ops = &cqspi_mem_ops; master->mem_caps = &cqspi_mem_caps; master->dev.of_node = pdev->dev.of_node; @@ -1686,7 +1686,7 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, cqspi->master_ref_clk_hz); if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) - master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; + master->buswidth_override_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) cqspi->use_direct_mode = true; if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
While trying to enable Octal SPI mode, it was observed that SPI_RX_OCTAL/SPI_TX_OCTAL were not propagating into the spi_device spi->mode setting. This was causing the SPI device to always operate in 1x mode instead of the desired 8x mode. Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> --- drivers/spi/spi-cadence-quadspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)