| Message ID | 20221124081221.1206167-4-mranostay@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: add 4x lane support for pci-j721e controllers | expand |
Hi Rob, I think your comment: https://lore.kernel.org/linux-pci/CAL_JsqJ5cOLXhD-73esmhVwMEWGT+w3SJC14Z0jY4tQJQRA7iw@mail.gmail.com was related to the commit log wording and not necessarily the actual diff. Please let me know if you are happy with this change and I shall merge the series. Thanks, Lorenzo On Thu, Nov 24, 2022 at 12:12:19AM -0800, Matt Ranostay wrote: > Add support for setting of two-bit field that allows selection of 4x lane > PCIe which was previously limited to only 2x lanes. > > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > --- > drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index 8990f58d64d5..dab3db9be6d8 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -42,7 +42,6 @@ enum link_status { > }; > > #define J721E_MODE_RC BIT(7) > -#define LANE_COUNT_MASK BIT(8) > #define LANE_COUNT(n) ((n) << 8) > > #define GENERATION_SEL_MASK GENMASK(1, 0) > @@ -52,6 +51,7 @@ struct j721e_pcie { > struct clk *refclk; > u32 mode; > u32 num_lanes; > + u32 max_lanes; > void __iomem *user_cfg_base; > void __iomem *intd_cfg_base; > u32 linkdown_irq_regfield; > @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, > { > struct device *dev = pcie->cdns_pcie->dev; > u32 lanes = pcie->num_lanes; > + u32 mask = GENMASK(8, 8); > u32 val = 0; > int ret; > > + if (pcie->max_lanes == 4) > + mask = GENMASK(9, 8); > + > val = LANE_COUNT(lanes - 1); > - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); > + ret = regmap_update_bits(syscon, offset, mask, val); > if (ret) > dev_err(dev, "failed to set link count\n"); > > @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) > ret = of_property_read_u32(node, "num-lanes", &num_lanes); > if (ret || num_lanes > data->max_lanes) > num_lanes = 1; > + > + pcie->max_lanes = data->max_lanes; > pcie->num_lanes = num_lanes; > > if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) > -- > 2.38.GIT >
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 8990f58d64d5..dab3db9be6d8 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = GENMASK(8, 8); u32 val = 0; int ret; + if (pcie->max_lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) ret = of_property_read_u32(node, "num-lanes", &num_lanes); if (ret || num_lanes > data->max_lanes) num_lanes = 1; + + pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))