From patchwork Sun Feb 28 21:25:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sjoerd Simons X-Patchwork-Id: 63178 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1097672lbc; Mon, 29 Feb 2016 00:05:26 -0800 (PST) X-Received: by 10.28.49.69 with SMTP id x66mr9441218wmx.11.1456733126537; Mon, 29 Feb 2016 00:05:26 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id hp6si30861849wjb.198.2016.02.29.00.05.26; Mon, 29 Feb 2016 00:05:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFAFBA75D7; Mon, 29 Feb 2016 09:05:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qt7zl63aAXud; Mon, 29 Feb 2016 09:05:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 75FC2A75E5; Mon, 29 Feb 2016 09:05:19 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 43F53A7559 for ; Mon, 29 Feb 2016 09:05:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GIWX-iWoUaYj for ; Mon, 29 Feb 2016 09:05:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by theia.denx.de (Postfix) with ESMTPS id 039D0A74A8 for ; Mon, 29 Feb 2016 09:05:09 +0100 (CET) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 32042266EAC Received: by dusk.luon.net (Postfix, from userid 1000) id 32A84232C5; Sun, 28 Feb 2016 22:25:06 +0100 (CET) From: Sjoerd Simons To: Simon Glass Date: Sun, 28 Feb 2016 22:25:01 +0100 Message-Id: <1456694706-911-8-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1456694706-911-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1456694706-911-1-git-send-email-sjoerd.simons@collabora.co.uk> Cc: Joe Hershberger , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 07/12] net: gmac_rk3288: Add RK3288 GMAC driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a new driver for the GMAC ethernet interface present in Rockchip RK3288 SOCs. This driver subclasses the generic design-ware driver to add the glue needed specifically for Rockchip. Signed-off-by: Sjoerd Simons --- Changes in v2: - Fix various coding style nits - Adjust to new hook name drivers/net/Kconfig | 7 +++ drivers/net/Makefile | 1 + drivers/net/gmac_rk3288.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/net/gmac_rk3288.c -- 2.7.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index bc2f51d..fa49856 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -133,4 +133,11 @@ config PIC32_ETH This driver implements 10/100 Mbps Ethernet and MAC layer for Microchip PIC32 microcontrollers. +config GMAC_RK3288 + bool "Rockchip RK3288 Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + This driver provides Rockchip RK3288 network support based on the + Synopsys Designware driver. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 33a81ee..d0a8009 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c new file mode 100644 index 0000000..5400b2c --- /dev/null +++ b/drivers/net/gmac_rk3288.c @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2015 Sjoerd Simons + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* * Rockchip GMAC ethernet IP driver for U-Boot */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "designware.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct gmac_rk3288_platdata { + struct dw_eth_pdata dw_eth_pdata; + int tx_delay; + int rx_delay; +}; + +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev) +{ + struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev); + + pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "tx_delay", 0x30); + pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "rx_delay", 0x10); + + return designware_eth_ofdata_to_platdata(dev); +} + +static int gmac_rk3288_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3288_grf *grf; + int clk; + + switch (priv->phydev->speed) { + case 10: + clk = GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = GMAC_CLK_SEL_25M; + break; + case 1000: + clk = GMAC_CLK_SEL_125M; + break; + default: + printf("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_clrsetreg(&grf->soc_con1, + GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT, + clk << GMAC_CLK_SEL_SHIFT); + + return 0; +} + +static int gmac_rk3288_probe(struct udevice *dev) +{ + int ret; + struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + struct rk3288_grf *grf; + struct udevice *clk; + + + ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &clk); + if (ret) + return ret; + + ret = clk_set_periph_rate(clk, SCLK_MAC, 0); + if (ret) + return ret; + + /* Set to RGMII mode */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + RMII_MODE_MASK << RMII_MODE_SHIFT | + GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT, + GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT); + + rk_clrsetreg(&grf->soc_con3, + RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT | + CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT | + CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT, + RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT | + pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT); + + priv->fix_mac_speed = gmac_rk3288_fix_mac_speed; + + return designware_eth_probe(dev); +} + +static const struct udevice_id rk3288_gmac_ids[] = { + { .compatible = "rockchip,rk3288-gmac" }, + { } +}; + +U_BOOT_DRIVER(eth_gmac_rk3288) = { + .name = "gmac_rk3288", + .id = UCLASS_ETH, + .of_match = rk3288_gmac_ids, + .ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata, + .probe = gmac_rk3288_probe, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};