| Message ID | 20221209123910.178609-1-konrad.dybcio@linaro.org |
|---|---|
| State | Accepted |
| Commit | 85d4e6ea082d3905f3ede470ac337fddc2d47650 |
| Headers | show |
| Series | clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clk | expand |
On 12/9/22 14:39, Konrad Dybcio wrote: > Just like in case of other SoCs change SDCC1/SDCC2 ops > to floor to avoid overclocking the controller. > > Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> > --- > drivers/clk/qcom/gcc-sm6115.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c > index 565f9912039f..5b8222fea2f7 100644 > --- a/drivers/clk/qcom/gcc-sm6115.c > +++ b/drivers/clk/qcom/gcc-sm6115.c > @@ -1258,7 +1258,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { > .name = "gcc_sdcc1_apps_clk_src", > .parent_data = gcc_parents_1, > .num_parents = ARRAY_SIZE(gcc_parents_1), > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_floor_ops, > }, > }; > > @@ -1305,7 +1305,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > .name = "gcc_sdcc2_apps_clk_src", > .parent_data = gcc_parents_11, > .num_parents = ARRAY_SIZE(gcc_parents_11), > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_floor_ops, > .flags = CLK_OPS_PARENT_ENABLE, > }, > };
On Fri, 9 Dec 2022 13:39:09 +0100, Konrad Dybcio wrote: > Just like in case of other SoCs change SDCC1/SDCC2 ops > to floor to avoid overclocking the controller. > > Applied, thanks! [1/1] clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clk commit: 85d4e6ea082d3905f3ede470ac337fddc2d47650 Best regards,
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 565f9912039f..5b8222fea2f7 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -1258,7 +1258,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -1305,7 +1305,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parents_11, .num_parents = ARRAY_SIZE(gcc_parents_11), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, .flags = CLK_OPS_PARENT_ENABLE, }, };
Just like in case of other SoCs change SDCC1/SDCC2 ops to floor to avoid overclocking the controller. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/clk/qcom/gcc-sm6115.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)