From patchwork Tue Mar 1 18:27:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Auger Eric X-Patchwork-Id: 63339 Delivered-To: patches@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1981780lbc; Tue, 1 Mar 2016 10:29:12 -0800 (PST) X-Received: by 10.28.214.6 with SMTP id n6mr440649wmg.49.1456856942866; Tue, 01 Mar 2016 10:29:02 -0800 (PST) Return-Path: Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com. [2a00:1450:400c:c09::22e]) by mx.google.com with ESMTPS id e18si38582623wjx.104.2016.03.01.10.29.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Mar 2016 10:29:02 -0800 (PST) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22e as permitted sender) client-ip=2a00:1450:400c:c09::22e; Authentication-Results: mx.google.com; spf=pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22e as permitted sender) smtp.mailfrom=eric.auger@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-wm0-x22e.google.com with SMTP id n186so50810812wmn.1 for ; Tue, 01 Mar 2016 10:29:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cujWFhUKexOiqR05DUZK+//zwamIkHJwZPLCxHcbnGY=; b=P4zx8Rku7KXVUMAI0I3wgTD6oJ+ROU6TgyxaJToyL9peAvdXuRizYaWLsPq3c3D2Nh SKNi8EGAcj0FwJoNUADdjScHwEhs0+noyA/azfFlYx6owKDcm9/zCQrPzClLMDhZmpHH +heeTrRbloFZIaSnYlqI/d32p2v/77w4JU5Yc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cujWFhUKexOiqR05DUZK+//zwamIkHJwZPLCxHcbnGY=; b=MsOsEHyxHUWHelYyFeWsk8igHYfxZnZUQy88mUiOVFW3YntAv+e/+f1o9Z1z9o9dhh zw4d8998Lr55YdfLM9ePDxCD0oRubPIKg1vmSoOOtI356BcAZWft1vZcqUDHLVXo7Iyd CFqM9o/RzCufQm+KIPsradS0HMQ1AykplHtaFl2PF6dG4z0WSfoS6H5JNVut/dtPWBXv jhKJwiUO5Nd7yRD0Ej/y/lRV8YfGmPlEXER7NXSZWlvuPQb7hP+q/Hk/0T8lFyEIqORt 5ceUQJRSQYLexWgFNhKEf/BOeDNhcU9luG1wp6wHBVxYUxR9vnohrr9AOInyEcRyzHnZ FBbw== X-Gm-Message-State: AD7BkJLF/ou+i2StkLnnL3gJ6np+VxuvC6iIwtL/RhYM99KQdGWOBMTxUHL7FAZAAiloCh2b5ps= X-Received: by 10.28.104.87 with SMTP id d84mr507287wmc.56.1456856942674; Tue, 01 Mar 2016 10:29:02 -0800 (PST) Return-Path: Received: from new-host-8.home (LMontsouris-657-1-37-90.w80-11.abo.wanadoo.fr. [80.11.198.90]) by smtp.gmail.com with ESMTPSA id k8sm32176385wjr.38.2016.03.01.10.29.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Mar 2016 10:29:01 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, robin.murphy@arm.com, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: suravee.suthikulpanit@amd.com, patches@linaro.org, linux-kernel@vger.kernel.org, Manish.Jaggi@caviumnetworks.com, Bharat.Bhushan@freescale.com, pranav.sawargaonkar@gmail.com, p.fedin@samsung.com, iommu@lists.linux-foundation.org Subject: [RFC v5 16/17] iommu/arm-smmu: do not advertise IOMMU_CAP_INTR_REMAP Date: Tue, 1 Mar 2016 18:27:56 +0000 Message-Id: <1456856877-4817-17-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456856877-4817-1-git-send-email-eric.auger@linaro.org> References: <1456856877-4817-1-git-send-email-eric.auger@linaro.org> Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu. Indeed the irq_remapping capability is abstracted on irqchip side for ARM as opposed to Intel IOMMU featuring IRQ remapping HW. So to check IRQ remapping capability, the msi domain needs to be checked instead. This commit needs to be applied after "vfio/type1: also check IRQ remapping capability at msi domain" else the legacy interrupt assignment gets broken with arm-smmu. Signed-off-by: Eric Auger --- drivers/iommu/arm-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c8b7e71..ce988fb 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1284,7 +1284,7 @@ static bool arm_smmu_capable(enum iommu_cap cap) */ return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + return false; /* interrupt translation handled at MSI controller level */ case IOMMU_CAP_NOEXEC: return true; default: