Message ID | 20221219094233.179153-4-xingyu.wu@starfivetech.com |
---|---|
State | New |
Headers | show |
Series | None | expand |
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c22e8f1d2640..cf981dce5bb9 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -433,5 +433,16 @@ uart5: serial@12020000 { reg-shift = <2>; status = "disabled"; }; + + wdog: watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + reset-names = "apb", "core"; + }; }; };
Add the watchdog node for the Starfive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)