diff mbox

[Xen-devel,v5,19/22] hvm/params: Add a new delivery type for event-channel in HVM_PARAM_CALLBACK_IRQ

Message ID 1457072152-16128-20-git-send-email-zhaoshenglong@huawei.com
State New
Headers show

Commit Message

Shannon Zhao March 4, 2016, 6:15 a.m. UTC
From: Shannon Zhao <shannon.zhao@linaro.org>

Add a new delivery type:
val[63:56] == 3: val[15:8] is flag: val[7:0] is a PPI.
To the flag, bit 8 stands the interrupt mode is edge(1) or level(0) and
bit 9 stands the interrupt polarity is active low(1) or high(0).

Cc: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
v5: fix the statement
---
 xen/include/public/hvm/params.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Julien Grall March 16, 2016, 3:03 p.m. UTC | #1
Hi Jan,

On 04/03/2016 10:16, Jan Beulich wrote:
>>>> On 04.03.16 at 07:15, <zhaoshenglong@huawei.com> wrote:

[...]

>> --- a/xen/include/public/hvm/params.h
>> +++ b/xen/include/public/hvm/params.h
>> @@ -55,6 +55,16 @@
>>    * if this delivery method is available.
>>    */
>>
>> +#define HVM_PARAM_CALLBACK_TYPE_EVENT    3
>> +/*
>> + * val[55:16] need to be zero.
>> + * val[15:8] is flag of event-channel interrupt:
>> + *  bit 8: interrupt is edge(1) or level(0) triggered
>> + *  bit 9: interrupt is active low(1) or high(0)
>> + * val[7:0] is PPI number used by event-channel.

is a PPI

>> + * This is only used by ARM/ARM64.
>> + */

[...]

> And then I'm now also wondering about the description of bits
> 8 and 9 - event channels don't know of edge/level triggering
> or high/low polarity, so it looks to me as if the comment is at
> least misleading too.

bit 8 and bit 9 are related to the PPI configuration. We need to know if 
the interrupt is level/edge trigger active low/high to configure 
correctly the interrupt controller.

What about renaming "interrupt" to "PPI" to make clear is related to the 
PPI?

Regards,
Julien Grall March 16, 2016, 4:34 p.m. UTC | #2
Hi Konrad,

On 04/03/2016 21:19, Konrad Rzeszutek Wilk wrote:
> Anyhow what I am wondering if there are some semantincs when it comes to PPI
> and it being able to 'mask' an vector until it exits or such? If so
> you should document that.

I'm not sure to understand what you are asking.

Xen takes advantage of the virtual interrupt controller to notify the 
guest of new pending event channels.

The life cycle (mask/eoi) of the interrupt associated to the 
notification is handled by the interrupt controller. The interrupt can't 
be re-entrant but we may receive spurious notification.

AFAIK, there is no specific semantics. Stefano, can you confirm it?

Regards,
diff mbox

Patch

diff --git a/xen/include/public/hvm/params.h b/xen/include/public/hvm/params.h
index 73d4718..2ea8d62 100644
--- a/xen/include/public/hvm/params.h
+++ b/xen/include/public/hvm/params.h
@@ -55,6 +55,16 @@ 
  * if this delivery method is available.
  */
 
+#define HVM_PARAM_CALLBACK_TYPE_EVENT    3
+/*
+ * val[55:16] need to be zero.
+ * val[15:8] is flag of event-channel interrupt:
+ *  bit 8: interrupt is edge(1) or level(0) triggered
+ *  bit 9: interrupt is active low(1) or high(0)
+ * val[7:0] is PPI number used by event-channel.
+ * This is only used by ARM/ARM64.
+ */
+
 /*
  * These are not used by Xen. They are here for convenience of HVM-guest
  * xenbus implementations.