| Message ID | 20221230113504.37032-11-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/aspeed_ast10x0: Map more peripherals & few more fixes | expand |
On 12/30/22 12:35, Philippe Mathieu-Daudé wrote: > This SoC uses a Cortex-M4F. QEMU only implements a M4, > which is good enough. Add a TODO note in case the M4F > is added. How complex would it be to add the FPU version of the M4 ? I suppose we have all the instructions already implemented ? > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/arm/aspeed_ast10x0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c > index 7a7443a95b..a3bcbef24a 100644 > --- a/hw/arm/aspeed_ast10x0.c > +++ b/hw/arm/aspeed_ast10x0.c > @@ -421,7 +421,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) > dc->realize = aspeed_soc_ast1030_realize; > > sc->name = "ast1030-a1"; > - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); > + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ > sc->silicon_rev = AST1030_A1_SILICON_REV; > sc->sram_size = 768 * KiB; > sc->secsram_size = 9 * KiB;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 7a7443a95b..a3bcbef24a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -421,7 +421,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) dc->realize = aspeed_soc_ast1030_realize; sc->name = "ast1030-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ sc->silicon_rev = AST1030_A1_SILICON_REV; sc->sram_size = 768 * KiB; sc->secsram_size = 9 * KiB;