diff mbox series

[3/3] arm64: dts: qcom: sm8250: Sort audio hw nodes

Message ID 20221230135044.287874-3-konrad.dybcio@linaro.org
State New
Headers show
Series [1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits | expand

Commit Message

Konrad Dybcio Dec. 30, 2022, 1:50 p.m. UTC 
Half of the audio hardware nodes were not sorted properly. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 142 +++++++++++++--------------
 1 file changed, 71 insertions(+), 71 deletions(-)

Comments

Krzysztof Kozlowski Dec. 30, 2022, 4:10 p.m. UTC | #1 
On 30/12/2022 14:50, Konrad Dybcio wrote:
> Half of the audio hardware nodes were not sorted properly. Fix that.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---


Just a note:

> +		wsamacro: codec@3240000 {
> +			compatible = "qcom,sm8250-lpass-wsa-macro";
> +			reg = <0 0x03240000 0 0x1000>;
> +			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
> +				 <&audiocc LPASS_CDC_WSA_NPL>,
> +				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +				 <&aoncc LPASS_CDC_VA_MCLK>,
> +				 <&vamacro>;
> +			clock-names = "mclk",
> +				      "npl",
> +				      "macro",
> +				      "dcodec",
> +				      "va",
> +				      "fsgen";
> +
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&wsa_swr_active>;
> +
> +			#clock-cells = <0>;
> +			clock-frequency = <9600000>;

This will conflict:
https://lore.kernel.org/all/20221224154255.43499-3-krzysztof.kozlowski@linaro.org/

https://lore.kernel.org/all/20221225115844.55126-3-krzysztof.kozlowski@linaro.org/

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index dffce681d417..0b6a6a809503 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2214,77 +2214,6 @@  tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
-		wsamacro: codec@3240000 {
-			compatible = "qcom,sm8250-lpass-wsa-macro";
-			reg = <0 0x03240000 0 0x1000>;
-			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
-				 <&audiocc LPASS_CDC_WSA_NPL>,
-				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&aoncc LPASS_CDC_VA_MCLK>,
-				 <&vamacro>;
-			clock-names = "mclk",
-				      "npl",
-				      "macro",
-				      "dcodec",
-				      "va",
-				      "fsgen";
-
-			pinctrl-names = "default";
-			pinctrl-0 = <&wsa_swr_active>;
-
-			#clock-cells = <0>;
-			clock-frequency = <9600000>;
-			clock-output-names = "mclk";
-			#sound-dai-cells = <1>;
-			status = "disabled";
-		};
-
-		swr0: soundwire-controller@3250000 {
-			compatible = "qcom,soundwire-v1.5.1";
-			reg = <0 0x03250000 0 0x2000>;
-			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&wsamacro>;
-			clock-names = "iface";
-
-			qcom,din-ports = <2>;
-			qcom,dout-ports = <6>;
-
-			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
-			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
-			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
-			qcom,ports-block-pack-mode =	/bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
-
-			#sound-dai-cells = <1>;
-			#address-cells = <2>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		audiocc: clock-controller@3300000 {
-			compatible = "qcom,sm8250-lpass-audiocc";
-			reg = <0 0x03300000 0 0x30000>;
-			#clock-cells = <1>;
-			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-			clock-names = "core", "audio", "bus";
-		};
-
-		vamacro: codec@3370000 {
-			compatible = "qcom,sm8250-lpass-va-macro";
-			reg = <0 0x03370000 0 0x1000>;
-			clocks = <&aoncc LPASS_CDC_VA_MCLK>,
-				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-			clock-names = "mclk", "macro", "dcodec";
-
-			#clock-cells = <0>;
-			clock-frequency = <9600000>;
-			clock-output-names = "fsgen";
-			#sound-dai-cells = <1>;
-		};
-
 		rxmacro: rxmacro@3200000 {
 			compatible = "qcom,sm8250-lpass-rx-macro";
 			reg = <0 0x03200000 0 0x1000>;
@@ -2388,6 +2317,77 @@  swr2: soundwire-controller@3230000 {
 			status = "disabled";
 		};
 
+		wsamacro: codec@3240000 {
+			compatible = "qcom,sm8250-lpass-wsa-macro";
+			reg = <0 0x03240000 0 0x1000>;
+			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
+				 <&audiocc LPASS_CDC_WSA_NPL>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&aoncc LPASS_CDC_VA_MCLK>,
+				 <&vamacro>;
+			clock-names = "mclk",
+				      "npl",
+				      "macro",
+				      "dcodec",
+				      "va",
+				      "fsgen";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&wsa_swr_active>;
+
+			#clock-cells = <0>;
+			clock-frequency = <9600000>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		swr0: soundwire-controller@3250000 {
+			compatible = "qcom,soundwire-v1.5.1";
+			reg = <0 0x03250000 0 0x2000>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&wsamacro>;
+			clock-names = "iface";
+
+			qcom,din-ports = <2>;
+			qcom,dout-ports = <6>;
+
+			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
+			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
+			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
+
+			#sound-dai-cells = <1>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		audiocc: clock-controller@3300000 {
+			compatible = "qcom,sm8250-lpass-audiocc";
+			reg = <0 0x03300000 0 0x30000>;
+			#clock-cells = <1>;
+			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "core", "audio", "bus";
+		};
+
+		vamacro: codec@3370000 {
+			compatible = "qcom,sm8250-lpass-va-macro";
+			reg = <0 0x03370000 0 0x1000>;
+			clocks = <&aoncc LPASS_CDC_VA_MCLK>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "mclk", "macro", "dcodec";
+
+			#clock-cells = <0>;
+			clock-frequency = <9600000>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
 		aoncc: clock-controller@3380000 {
 			compatible = "qcom,sm8250-lpass-aoncc";
 			reg = <0 0x03380000 0 0x40000>;