From patchwork Wed Jan 25 04:42:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 6389 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 38F4323E12 for ; Wed, 25 Jan 2012 04:43:27 +0000 (UTC) Received: from mail-bk0-f52.google.com (mail-bk0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 29653A18808 for ; Wed, 25 Jan 2012 04:43:27 +0000 (UTC) Received: by mail-bk0-f52.google.com with SMTP id r19so4923213bka.11 for ; Tue, 24 Jan 2012 20:43:27 -0800 (PST) MIME-Version: 1.0 Received: by 10.205.134.129 with SMTP id ic1mr6172295bkc.92.1327466606902; Tue, 24 Jan 2012 20:43:26 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.130.220 with SMTP id u28cs124901bks; Tue, 24 Jan 2012 20:43:26 -0800 (PST) Received: by 10.68.116.144 with SMTP id jw16mr37265790pbb.28.1327466604511; Tue, 24 Jan 2012 20:43:24 -0800 (PST) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id e6si23786794pbd.94.2012.01.24.20.43.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jan 2012 20:43:24 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by dado15 with SMTP id o15so3645678dad.37 for ; Tue, 24 Jan 2012 20:43:23 -0800 (PST) Received: by 10.68.115.133 with SMTP id jo5mr37033037pbb.50.1327466603392; Tue, 24 Jan 2012 20:43:23 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f3sm3287217pbq.4.2012.01.24.20.43.19 (version=SSLv3 cipher=OTHER); Tue, 24 Jan 2012 20:43:22 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH v5 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Date: Wed, 25 Jan 2012 10:12:59 +0530 Message-Id: <1327466582-11816-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327466582-11816-1-git-send-email-chander.kashyap@linaro.org> References: <1327466582-11816-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQktDTr7qL9B3Uo4I0IAVJt7xpij6AtaHl6llKIla87BIpkcH4GUWdd7teHJ/1t6alDH5ObW CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- Changes for v2: - None Changes for v3: - None Changes for V4: - Added CONFIG_SYS_CLK_FREQ to trats.h Changes for v5: - None arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + include/configs/trats.h | 1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index be000cb..8286680 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -49,6 +49,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/trats.h b/include/configs/trats.h index acb3241..10f11d9 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -49,6 +49,7 @@ /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG