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[2001:1868:205::9]) by mx.google.com with ESMTPS id v13si314734pas.199.2016.03.17.03.13.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Mar 2016 03:13:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1agUuJ-0005Qh-8F; Thu, 17 Mar 2016 10:11:55 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1agUsa-0002KJ-Nx for linux-arm-kernel@lists.infradead.org; Thu, 17 Mar 2016 10:10:14 +0000 Received: from 172.24.1.36 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.36]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DDR55524; Thu, 17 Mar 2016 18:08:57 +0800 (CST) Received: from linux-ibm.site (10.175.102.37) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 17 Mar 2016 18:08:48 +0800 From: Kefeng Wang To: Catalin Marinas , Will Deacon Subject: [RFC PATCH] arm64: Expose physical/virtual address bits through cpuinfo Date: Thu, 17 Mar 2016 18:08:03 +0800 Message-ID: <1458209283-44999-1-git-send-email-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 1.7.12.4 MIME-Version: 1.0 X-Originating-IP: [10.175.102.37] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.56EA8239.01F5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a0cfd38d199305f757fa54d5a2d35383 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160317_031009_624323_32146162 X-CRM114-Status: GOOD ( 12.23 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [119.145.14.65 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , wangkefeng.wang@huawei.com, linux-arm-kernel@lists.infradead.org, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org AArch64 support six types Physical Address range, permitted values in ID_AA64MMFR0_EL1 are: 0000 32 bits, 4GB. 0001 36 bits, 64GB. 0010 40 bits, 1TB. 0011 42 bits, 4TB. 0100 44 bits, 16TB. 0101 48 bits, 256TB. All other values are reserved. Meanwhile, AArch64 allows 36-bit, 39-bit, 42-bit, 47-bit and 48-bit virtual addresses. Exposing the physical and virtual address bits to userspace through procfs like x86, then it is easy to check them from cpuinfo. Signed-off-by: Kefeng Wang --- arch/arm64/include/asm/cpufeature.h | 11 +++++++++++ arch/arm64/kernel/cpuinfo.c | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) -- 1.7.12.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index a5c769b..33a9dc5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -188,6 +188,17 @@ static inline bool system_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); } +static inline int id_aa64mmfr0_parange_bits(void) +{ + /* + * PARange[3:0] allows 0~5, other values are reserved, + * convert to physical address bits with a simple formula. + */ + u32 parange = read_system_reg(SYS_ID_AA64MMFR0_EL1) & 0xf; + + return parange < 3 ? 32 + parange * 4 : 42 + (parange - 3) * (parange - 2); +} + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 212ae63..f6b49db 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -146,7 +146,9 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "CPU architecture: 8\n"); seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); - seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); + seq_printf(m, "CPU revision\t: %d\n", MIDR_REVISION(midr)); + seq_printf(m, "address sizes\t: %d bits physical, %d bits virtual\n\n", + id_aa64mmfr0_parange_bits(), VA_BITS); } return 0;