From patchwork Thu Mar 17 13:20:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 63992 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp465087lbc; Thu, 17 Mar 2016 06:22:04 -0700 (PDT) X-Received: by 10.98.1.197 with SMTP id 188mr15042483pfb.8.1458220924483; Thu, 17 Mar 2016 06:22:04 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id p11si2956190par.197.2016.03.17.06.22.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Mar 2016 06:22:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0AA441A1E24; Thu, 17 Mar 2016 06:22:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22d.google.com (mail-wm0-x22d.google.com [IPv6:2a00:1450:400c:c09::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DA4321A1E23 for ; Thu, 17 Mar 2016 06:22:22 -0700 (PDT) Received: by mail-wm0-x22d.google.com with SMTP id l68so226097387wml.0 for ; Thu, 17 Mar 2016 06:22:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aO+dFPlXfxbDZiM8rNV8heyd7gvvALhOIoY6JF0rlh4=; b=ZX7yclDy1RtP2PL3GZcqbXLYRHPnmglNVGKMibMRCvEBCD2gL3UKET5+hdosIJqgul 2HEkqe8MGJAcXC7ZNvKISLeBy1hoYNSrYzEWcudCOiZxipjUP83s9fGfrS+qDJNB8Lsi /fwhOBT2Lt4scN9HP/S+ghGST9waB4FMwPgAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aO+dFPlXfxbDZiM8rNV8heyd7gvvALhOIoY6JF0rlh4=; b=Yr5dg7wvhvSpmz/z6ZE5QJrAOsV0BSBQ3BYlzq1i/6wU7dwRrC/hkMg10lG/JFg85/ peTyp3naU3w8fmEPRg+dDGF49m4lm8xN/8GcInSvlqV3mETqTHaZCRG3tALHhOYuaPJ5 Oj4oUGeViGT1Z/27+vMNacX8uKc1sxJM+Xb9qSNqxrNC/cdhQjwLTFbgYsZnHM655Af3 uEwupSQdkYzuUTn3rL5j5WosM9X7HKESWRpjtA6+eK93T6vOTDccWkJmdO+vLdx1TN6P rLGFDc/UcGUPtU5GmdAU9UefXXYWD4i2oGaNjcrZ0mXwn3qIJT21d25S2VyUr1MT/I1P JUgg== X-Gm-Message-State: AD7BkJKOwhn/tfR+k548hc/lKsB41+G7JN1eJRKqp/Br6n8QrzNeDVbKKtzo8Q2GTQOMRtlN X-Received: by 10.28.147.72 with SMTP id v69mr34243555wmd.79.1458220921567; Thu, 17 Mar 2016 06:22:01 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id v5sm30198913wmg.16.2016.03.17.06.20.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Mar 2016 06:22:00 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Date: Thu, 17 Mar 2016 14:20:11 +0100 Message-Id: <1458220815-6944-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> References: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 3/7] ArmPkg/ArmExceptionLib: stack FPSR on common path X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" We have three code paths to stack/unstack the exception context, one for each of EL3, EL2 and EL1. However, they all access the same copy of FPSR so move that access to the common path. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) -- 2.5.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index c47974b81e8b..3117e710fa53 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -286,26 +286,25 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x1) 1:mrs x1, elr_el1 // Exception Link Register mrs x2, spsr_el1 // Saved Processor Status Register 32bit - mrs x3, fpsr // Floating point Status Register 32bit mrs x4, esr_el1 // EL1 Exception syndrome register 32bit mrs x5, far_el1 // EL1 Fault Address Register b 4f 2:mrs x1, elr_el2 // Exception Link Register mrs x2, spsr_el2 // Saved Processor Status Register 32bit - mrs x3, fpsr // Floating point Status Register 32bit mrs x4, esr_el2 // EL2 Exception syndrome register 32bit mrs x5, far_el2 // EL2 Fault Address Register b 4f 3:mrs x1, elr_el3 // Exception Link Register mrs x2, spsr_el3 // Saved Processor Status Register 32bit - mrs x3, fpsr // Floating point Status Register 32bit mrs x4, esr_el3 // EL3 Exception syndrome register 32bit mrs x5, far_el3 // EL3 Fault Address Register +4:mrs x3, fpsr // Floating point Status Register 32bit + // Adjust SP to save next set -4:add sp, sp, #FP_CONTEXT_SIZE + add sp, sp, #FP_CONTEXT_SIZE // Push FP regs to Stack. ALL_FP_REGS @@ -357,22 +356,21 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x6) 1:msr elr_el1, x1 // Exception Link Register msr spsr_el1,x2 // Saved Processor Status Register 32bit - msr fpsr, x3 // Floating point Status Register 32bit msr esr_el1, x4 // EL1 Exception syndrome register 32bit msr far_el1, x5 // EL1 Fault Address Register b 4f 2:msr elr_el2, x1 // Exception Link Register msr spsr_el2,x2 // Saved Processor Status Register 32bit - msr fpsr, x3 // Floating point Status Register 32bit msr esr_el2, x4 // EL2 Exception syndrome register 32bit msr far_el2, x5 // EL2 Fault Address Register b 4f 3:msr elr_el3, x1 // Exception Link Register msr spsr_el3,x2 // Saved Processor Status Register 32bit - msr fpsr, x3 // Floating point Status Register 32bit msr esr_el3, x4 // EL3 Exception syndrome register 32bit msr far_el3, x5 // EL3 Fault Address Register -4:// pop all regs and return from exception. +4:msr fpsr, x3 // Floating point Status Register 32bit + + // pop all regs and return from exception. sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) ALL_GP_REGS