From patchwork Thu Mar 17 13:20:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 63993 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp465113lbc; Thu, 17 Mar 2016 06:22:06 -0700 (PDT) X-Received: by 10.98.18.212 with SMTP id 81mr14949969pfs.104.1458220926645; Thu, 17 Mar 2016 06:22:06 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id e72si12529433pfb.126.2016.03.17.06.22.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Mar 2016 06:22:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 437201A1E3B; Thu, 17 Mar 2016 06:22:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 99F501A1E38 for ; Thu, 17 Mar 2016 06:22:24 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id p65so117183592wmp.0 for ; Thu, 17 Mar 2016 06:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ymv09tbK5Favsi39THegj7lBbsd6zuBy4PHS9qvpGT8=; b=R2aaLhFinQmMIY0aVUKmDbuxegV9jPXtCr27+21WRM5BlL+hxArCIYV2zm6VTQXZGx qQ50wxemgqgwIwGb9ApFA5WJ5W/XhtREArxCpupNoO767/KLBkw95y1bpUmlu6lFRWBA Hb1xLCNa+0RPH73vxRaU9h3CGq077rBA3j3bw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ymv09tbK5Favsi39THegj7lBbsd6zuBy4PHS9qvpGT8=; b=bqcKE1LdgQX42WrAmHokrDL0XtLby5zR19jjjsEWnTt358w7b+Vl0gkbDZ2slzDwQG krB4dg/rXNX9yijtwIQtyw3B+KNxWhQFTC4RF4UOT7CtritkYArVRXbhU84PawwERb0e FMryt3wt/xMQofCrpL1NK9jzxYfPZLkvoziX/CRAeKvSPnK2/HIpjt2I/lIwl3fDBpt0 sT8sUHRKE6ioOhS12UhV5jPWkKtRw5zjVexPTo9BuujGbtA0nfWXKdARDRUCOOd3YbuH j7FZC5UKsGYmjG2mtRZ/xX2s3QupU5fVfc+Qt9AFHKKpUVjH2xYHuEX8hJii/c+/a7oZ 3XPA== X-Gm-Message-State: AD7BkJKlS83Cf8sYXbwtmB77iGy27pRZg49VjbZDsag9nfTi26hFHrfooSuG3WwpXGy4Z/Vw X-Received: by 10.194.113.130 with SMTP id iy2mr9995961wjb.56.1458220923338; Thu, 17 Mar 2016 06:22:03 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id v5sm30198913wmg.16.2016.03.17.06.22.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Mar 2016 06:22:02 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Date: Thu, 17 Mar 2016 14:20:12 +0100 Message-Id: <1458220815-6944-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> References: <1458220815-6944-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 4/7] ArmPkg/ArmExceptionLib: don't restore ESR and FAR upon exception return X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" ESR and FAR are populated by the hardware upon exception entry, and describe the exception, not the interrupted context. So there is no point in restoring their values before returning from the exception. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 6 ------ 1 file changed, 6 deletions(-) -- 2.5.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index 3117e710fa53..c7ea061a93ea 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -356,18 +356,12 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x6) 1:msr elr_el1, x1 // Exception Link Register msr spsr_el1,x2 // Saved Processor Status Register 32bit - msr esr_el1, x4 // EL1 Exception syndrome register 32bit - msr far_el1, x5 // EL1 Fault Address Register b 4f 2:msr elr_el2, x1 // Exception Link Register msr spsr_el2,x2 // Saved Processor Status Register 32bit - msr esr_el2, x4 // EL2 Exception syndrome register 32bit - msr far_el2, x5 // EL2 Fault Address Register b 4f 3:msr elr_el3, x1 // Exception Link Register msr spsr_el3,x2 // Saved Processor Status Register 32bit - msr esr_el3, x4 // EL3 Exception syndrome register 32bit - msr far_el3, x5 // EL3 Fault Address Register 4:msr fpsr, x3 // Floating point Status Register 32bit // pop all regs and return from exception.