diff mbox series

[01/12] crypto: axis - do not DMA to ahash_request.result

Message ID 20230110135042.2940847-2-vincent.whitchurch@axis.com
State New
Headers show
Series crypto: axis - make tests pass | expand

Commit Message

Vincent Whitchurch Jan. 10, 2023, 1:50 p.m. UTC 
From: Lars Persson <larper@axis.com>

The crypto API does not promise that the result pointer is suitable
for DMA.  Use an intermediate result buffer and let the CPU copy the
digest to the ahash_request.

Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
---
 drivers/crypto/axis/artpec6_crypto.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

Comments

Herbert Xu Jan. 20, 2023, 9:09 a.m. UTC | #1 
On Tue, Jan 10, 2023 at 02:50:31PM +0100, Vincent Whitchurch wrote:
>
> @@ -2216,6 +2220,14 @@ static void artpec6_crypto_complete_aead(struct crypto_async_request *req)
>  
>  static void artpec6_crypto_complete_hash(struct crypto_async_request *req)
>  {
> +	struct ahash_request *areq = container_of(req, struct ahash_request, base);
> +	struct artpec6_hash_request_context *ctx = ahash_request_ctx(areq);
> +	struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
> +	size_t digestsize = crypto_ahash_digestsize(ahash);
> +
> +	if (ctx->hash_flags & HASH_FLAG_FINALIZED)
> +		memcpy(areq->result, ctx->digeststate, digestsize);
> +

I was just looking through the driver and digeststate does not
appear to be aligned to the DMA cacheline, should it be?

Thanks,
Vincent Whitchurch Jan. 27, 2023, 3:35 p.m. UTC | #2 
On Fri, Jan 20, 2023 at 10:09:18AM +0100, Herbert Xu wrote:
> On Tue, Jan 10, 2023 at 02:50:31PM +0100, Vincent Whitchurch wrote:
> >
> > @@ -2216,6 +2220,14 @@ static void artpec6_crypto_complete_aead(struct crypto_async_request *req)
> >  
> >  static void artpec6_crypto_complete_hash(struct crypto_async_request *req)
> >  {
> > +	struct ahash_request *areq = container_of(req, struct ahash_request, base);
> > +	struct artpec6_hash_request_context *ctx = ahash_request_ctx(areq);
> > +	struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
> > +	size_t digestsize = crypto_ahash_digestsize(ahash);
> > +
> > +	if (ctx->hash_flags & HASH_FLAG_FINALIZED)
> > +		memcpy(areq->result, ctx->digeststate, digestsize);
> > +
> 
> I was just looking through the driver and digeststate does not
> appear to be aligned to the DMA cacheline, should it be?

Yes, you're right, thanks, that buffer and a few others are missing
alignment annotations.  I'll add a patch to fix that when I respin the
series.
diff mbox series

Patch

diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c
index 51c66afbe677..87af44ac3e64 100644
--- a/drivers/crypto/axis/artpec6_crypto.c
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -276,6 +276,7 @@  enum artpec6_crypto_hash_flags {
 	HASH_FLAG_FINALIZE = 8,
 	HASH_FLAG_HMAC = 16,
 	HASH_FLAG_UPDATE_KEY = 32,
+	HASH_FLAG_FINALIZED = 64,
 };
 
 struct artpec6_crypto_req_common {
@@ -1493,12 +1494,15 @@  static int artpec6_crypto_prepare_hash(struct ahash_request *areq)
 			return error;
 
 		/* Descriptor for the final result */
-		error = artpec6_crypto_setup_in_descr(common, areq->result,
+		error = artpec6_crypto_setup_in_descr(common,
+						      req_ctx->digeststate,
 						      digestsize,
 						      true);
 		if (error)
 			return error;
 
+		req_ctx->hash_flags |= HASH_FLAG_FINALIZED;
+
 	} else { /* This is not the final operation for this request */
 		if (!run_hw)
 			return ARTPEC6_CRYPTO_PREPARE_HASH_NO_START;
@@ -2216,6 +2220,14 @@  static void artpec6_crypto_complete_aead(struct crypto_async_request *req)
 
 static void artpec6_crypto_complete_hash(struct crypto_async_request *req)
 {
+	struct ahash_request *areq = container_of(req, struct ahash_request, base);
+	struct artpec6_hash_request_context *ctx = ahash_request_ctx(areq);
+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
+	size_t digestsize = crypto_ahash_digestsize(ahash);
+
+	if (ctx->hash_flags & HASH_FLAG_FINALIZED)
+		memcpy(areq->result, ctx->digeststate, digestsize);
+
 	req->complete(req, 0);
 }