PCI: cadence: Fix next function value in case of ARI

From: Jasko-EXT Wojciech <wojciech.jasko-EXT@continental-corporation.com>

Next function field in ARI_CAP_AND_CTR field register for last
function should be zero but thats not the case, so this patch
programs the next function field for last function as zero.

Signed-off-by: Jasko-EXT Wojciech <wojciech.jasko-EXT@continental-corporation.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-ep.c | 15 ++++++++++++++-
 drivers/pci/controller/cadence/pcie-cadence.h    |  6 ++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

On Wed, Jan 18, 2023 at 12:50:35PM +0530, Achal Verma wrote:
> From: Jasko-EXT Wojciech <wojciech.jasko-EXT@continental-corporation.com>
> 
> Next function field in ARI_CAP_AND_CTR field register for last
> function should be zero but thats not the case, so this patch
> programs the next function field for last function as zero.

s/thats/that's/

When you fix the comment formatting, also update the commit log to be
imperative style and use the terms from the spec, e.g.,

  Clear the ARI Capability Next Function Number of the last function.

ARI_CAP_AND_CTR is a Cadence-specific name (and doesn't seem to appear
even in that driver).  The commit log should use the PCIe term.

See https://chris.beams.io/posts/git-commit/

> Signed-off-by: Jasko-EXT Wojciech <wojciech.jasko-EXT@continental-corporation.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-ep.c | 15 ++++++++++++++-
>  drivers/pci/controller/cadence/pcie-cadence.h    |  6 ++++++
>  2 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index b8b655d4047e..6b6904cf0123 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
>  	struct cdns_pcie *pcie = &ep->pcie;
>  	struct device *dev = pcie->dev;
>  	int max_epfs = sizeof(epc->function_num_map) * 8;
> -	int ret, value, epf;
> +	int ret, epf, last_fn;
> +	u32 reg, value;
>  
>  	/*
>  	 * BIT(0) is hardwired to 1, hence function 0 is always enabled
> @@ -573,6 +574,18 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
>  	 */
>  	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);
>  
> +	/* Setup ARI Next Function Number.
> +	 * This field should point to the next physical Function and 0 for
> +	 * last Function.
> +	 */
> +	last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG);
> +	reg     = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn);
> +
> +	// Clear Next Function Number for the last function used.
> +	value  = cdns_pcie_readl(pcie, reg);
> +	value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK;
> +	cdns_pcie_writel(pcie, reg, value);
> +
>  	if (ep->quirk_disable_flr) {
>  		for (epf = 0; epf < max_epfs; epf++) {
>  			if (!(epc->function_num_map & BIT(epf)))
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 190786e47df9..68c4c7878111 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -130,6 +130,12 @@
>  #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET	0xc0
>  #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET	0x200
>  
> +/*
> + * Endpoint PF Registers
> + */
> +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn)	(0x144 + (fn) * 0x1000)
> +#define CDNS_PCIE_ARI_CAP_NFN_MASK	GENMASK(15, 8)
> +
>  /*
>   * Root Port Registers (PCI configuration space for the root port function)
>   */
> -- 
> 2.25.1
> 
> 
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