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[2001:1868:205::9]) by mx.google.com with ESMTPS id lk8si627986pab.112.2016.03.25.02.38.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Mar 2016 02:38:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajOBS-0005oi-5s; Fri, 25 Mar 2016 09:37:34 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajOAy-0005dZ-J1 for linux-arm-kernel@lists.infradead.org; Fri, 25 Mar 2016 09:37:07 +0000 Received: from 172.24.1.60 (EHLO szxeml430-hub.china.huawei.com) ([172.24.1.60]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DHP56267; Fri, 25 Mar 2016 17:36:00 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.235.1; Fri, 25 Mar 2016 17:35:47 +0800 From: Kefeng Wang To: Catalin Marinas , "Suzuki K . Poulose" Subject: [RFC PATCH 2/3] arm64: Expose physical/virtual address bits through cpuinfo Date: Fri, 25 Mar 2016 17:30:08 +0800 Message-ID: <1458898209-7486-3-git-send-email-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 2.6.0.GIT In-Reply-To: <1458898209-7486-1-git-send-email-wangkefeng.wang@huawei.com> References: <1458898209-7486-1-git-send-email-wangkefeng.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.56F50681.0071, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 22c96f0f7aa23c6ac40ad7d46d0fca7e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160325_023705_356549_88ED81D9 X-CRM114-Status: GOOD ( 11.14 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , wangkefeng.wang@huawei.com, Will Deacon , linux-arm-kernel@lists.infradead.org, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org ARMv8 Physical Address range allows 0x0~0x6, the 0x6 is supported in ARMv8.2, permitted values in ID_AA64MMFR0_EL1 are: 0000 32 bits, 4GB. 0001 36 bits, 64GB. 0010 40 bits, 1TB. 0011 42 bits, 4TB. 0100 44 bits, 16TB. 0101 48 bits, 256TB. 0110 52 bits, 4096TB. All other values are reserved. Meanwhile, ARMv8 can support 48bit or 52bit virtual addresses, larger virtual address(52bit) is introduced in ARMv8.2. Exposing the physical and virtual address bits to userspace through procfs like x86, then it is easy to check the capacity of them that cpu supported from cpuinfo. Signed-off-by: Kefeng Wang --- arch/arm64/include/asm/cpufeature.h | 18 ++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 6 +++++- 2 files changed, 23 insertions(+), 1 deletion(-) -- 1.7.12.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index b9b6494..5b2c206 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -170,6 +170,24 @@ static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; } +static inline u8 get_parange_bits(u64 mmfr0) +{ + /* + * PARange[3:0] allows 0x0~0x6, the 0x6 introduced to support 52bit PA + * in ARMv8.2, other values are reserved. + */ + u8 pa_bits[] = {32, 36, 40, 42, 44, 48, 52}; + int fld = cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_PARANGE_SHIFT); + return pa_bits[fld]; +} + +static inline u8 get_varange_bits(u64 mmfr2) +{ + /* 52bit Larger virtual address supported in ARMv8.2 */ + int fld = cpuid_feature_extract_unsigned_field(mmfr2, ID_AA64MMFR2_LVA_SHIFT); + return fld == 0x1 ? 52 : 48; +} + void __init setup_cpu_features(void); void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 84c8684..488d49a 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -107,6 +107,8 @@ static int c_show(struct seq_file *m, void *v) for_each_online_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); u32 midr = cpuinfo->reg_midr; + u64 mmfr0 = cpuinfo->reg_id_aa64mmfr0; + u64 mmfr2 = cpuinfo->reg_id_aa64mmfr2; /* * glibc reads /proc/cpuinfo to determine the number of @@ -148,7 +150,9 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "CPU architecture: 8\n"); seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); - seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); + seq_printf(m, "CPU revision\t: %d\n", MIDR_REVISION(midr)); + seq_printf(m, "address sizes\t: %d bits physical, %d bits virtual\n\n", + get_parange_bits(mmfr0), get_varange_bits(mmfr2)); } return 0;