| Message ID | 20230124131717.128660-4-bchihi@baylibre.com |
|---|---|
| State | Accepted |
| Commit | 89b045d3c2cdffbb62f81c659e69653d862feee3 |
| Headers | show |
| Series | Add LVTS thermal architecture | expand |
On 24/01/2023 14:17, bchihi@baylibre.com wrote: > From: Balsam CHIHI <bchihi@baylibre.com> > > Add efuse node. > This will be required by the thermal driver to get the calibration data. > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> I fixed the subject prefix to: arm64: dts: mt8195: ... to be in line with other commits. Please take that into account for future patches you send. Applied thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 5d31536f4c48..09df105f4606 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { > dp_calibration: dp-data@1ac { > reg = <0x1ac 0x10>; > }; > + lvts_efuse_data1: lvts1-calib@1bc { > + reg = <0x1bc 0x14>; > + }; > + lvts_efuse_data2: lvts2-calib@1d0 { > + reg = <0x1d0 0x38>; > + }; > }; > > u3phy2: t-phy@11c40000 {
On Wed, Jan 25, 2023 at 3:25 PM Matthias Brugger <matthias.bgg@gmail.com> wrote: > > > > On 24/01/2023 14:17, bchihi@baylibre.com wrote: > > From: Balsam CHIHI <bchihi@baylibre.com> > > > > Add efuse node. > > This will be required by the thermal driver to get the calibration data. > > > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > I fixed the subject prefix to: > arm64: dts: mt8195: ... > to be in line with other commits. > Please take that into account for future patches you send. > > Applied thanks! > Hi Matthias, Thank you for the fix and for applying the patch! Best regards, Balsam > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 5d31536f4c48..09df105f4606 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { > > dp_calibration: dp-data@1ac { > > reg = <0x1ac 0x10>; > > }; > > + lvts_efuse_data1: lvts1-calib@1bc { > > + reg = <0x1bc 0x14>; > > + }; > > + lvts_efuse_data2: lvts2-calib@1d0 { > > + reg = <0x1d0 0x38>; > > + }; > > }; > > > > u3phy2: t-phy@11c40000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..09df105f4606 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { dp_calibration: dp-data@1ac { reg = <0x1ac 0x10>; }; + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; }; u3phy2: t-phy@11c40000 {