Message ID | 1675318653-28352-6-git-send-email-quic_srivasam@quicinc.com |
---|---|
State | New |
Headers | show |
Series | Add resets for ADSP based audio clock controller driver | expand |
Quoting Srinivasa Rao Mandadapu (2023-02-01 22:17:33) > Skip lpass_aon_cc_pll configuration for ADSP based platforms > based on qcom,adsp-pil-mode property. > This is to avoid ADSP out of reset fail. > > Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> > Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c index 8e2f433..76611a3 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -847,7 +847,13 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev) goto exit; } - clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config); + /* + * ADSP firmware is in control of this PLL frequency when + * remoteproc is used. Skip frequency configuration in that + * case. + */ + if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) + clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config); ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap); if (ret) {