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[2/3] x86/umwait: Increase tpause and umwait quanta

Message ID 20230306123418.720679-3-dedekind1@gmail.com
State New
Headers show
Series Sapphire Rapids C0.x idle states support | expand

Commit Message

Artem Bityutskiy March 6, 2023, 12:34 p.m. UTC 
From: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

== Background ==

The 'umwait' and 'tpause' instructions both put the CPU in a low power
state while they wait.  They amount of time they wait is influenced by
an explicit deadline value passed in a register and an implicit value
written to an shared MSR (MSR_IA32_UMWAIT_CONTROL).

Existing 'tpause' users (udelay()) can tolerate a wide range of
MSR_IA32_UMWAIT_CONTROL MSR values.  The explicit deadline trumps the
MSR for short delays.  Longer delays will see extra wakeups, but no
functional issues.

== Problem ==

Extra wakeups mean extra power.  That translates into worse idle power
when 'umwait' gets used for idle.

== Solution ==

Increase MSR_IA32_UMWAIT_CONTROL by factor of 100 to decrease idle power
when using 'umwait'.  Make 'tpause' rely on its explicit deadline more
often and reduce the number of wakeups and save power during long delays.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
---
 arch/x86/kernel/cpu/umwait.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index ec8064c0ae03..17c23173da0f 100644
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
@@ -14,9 +14,9 @@ 
 
 /*
  * Cache IA32_UMWAIT_CONTROL MSR. This is a systemwide control. By default,
- * umwait max time is 100000 in TSC-quanta and C0.2 is enabled
+ * umwait max time is 10,000,000 in TSC-quanta and C0.2 is enabled.
  */
-static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE);
+static u32 umwait_control_cached = UMWAIT_CTRL_VAL(10000000, UMWAIT_C02_ENABLE);
 
 /*
  * Cache the original IA32_UMWAIT_CONTROL MSR value which is configured by