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SoCFPGA with CONFIG_THUMB2_KERNEL boot error

Message ID CAKv+Gu8dmYDqri7Nt_A6vKTQo1eqFa7G=wdYQ8ad7EaT_smA7Q@mail.gmail.com
State New
Headers show

Commit Message

Ard Biesheuvel April 20, 2016, 11:06 a.m. UTC 
On 20 April 2016 at 13:00, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Wed, Apr 20, 2016 at 12:26:22PM +0200, Ard Biesheuvel wrote:

>> On 20 April 2016 at 11:55, Sascha Hauer <s.hauer@pengutronix.de> wrote:

>> > On Wed, Apr 20, 2016 at 11:43:30AM +0200, Ard Biesheuvel wrote:

>> >> (replying to self)

>> >>

>> >> On 20 April 2016 at 11:39, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:

>> >> > (+ Arnd)

>> >> >

>> >> > On 20 April 2016 at 11:25, Dave Martin <Dave.Martin@arm.com> wrote:

>> >> >> On Tue, Apr 19, 2016 at 04:02:20PM +0200, Steffen Trumtrar wrote:

>> >> >>> Hi!

>> >> >>>

>> >> >>> According to kernelci.org (and validating on my own hardware), the current

>> >> >>> socfpga mainline kernel has an issue with CONFIG_THUMB2_KERNEL enabled.

>> >> >>>

>> >> >>> https://storage.kernelci.org/mainline/v4.6-rc4-11-g12566cc35d0e/arm-multi_v7_defconfig/lab-khilman/boot-socfpga_cyclone5_de0_sockit.html

>> >> >>>

>> >> >>> vs

>> >> >>>

>> >> >>> https://storage.kernelci.org/mainline/v4.6-rc4-11-g12566cc35d0e/arm-multi_v7_defconfig+CONFIG_THUMB2_KERNEL=y/lab-khilman/boot-socfpga_cyclone5_de0_sockit.html

>> >> >>>

>> >> >>> Both boot successfully, but notice that the board fails to bring up CPU1 if

>> >> >>> thumb2 support is enabled.

>> >> >>>

>> >> >>> Any ideas why this might be happening?

>> >> >>

>> >>

>> >> Actually, this looks like a problem with the secondary entry point to

>> >> me. Could you try this?

>> >

>> > Been there, done that. Unfortunately this does not solve the problem.

>> >

>>

>> How about if you put this on top?

>>

>> diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S

>> index 5d94b7a2fb10..c160fa3007e9 100644

>> --- a/arch/arm/mach-socfpga/headsmp.S

>> +++ b/arch/arm/mach-socfpga/headsmp.S

>> @@ -13,6 +13,7 @@

>>  #include <asm/assembler.h>

>>

>>         .arch   armv7-a

>> +       .arm

>

> \o/

>

> This did the trick, it now boots with two cpus up. Thanks for looking

> into this issue.

>

> I'll create a patch for this.

>


Great. I think just the last part may be sufficient, since the bx r4
in headsmp.S will do an interworking branch to Thumb2

Also, I noticed that the code in headsmp.S looks a bit strange. You
should really only need this:

-------8<-----------

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Comments

Ard Biesheuvel April 21, 2016, 6:24 a.m. UTC | #1 
On 21 April 2016 at 01:51, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Wed, Apr 20, 2016 at 01:06:28PM +0200, Ard Biesheuvel wrote:

>> @@ -21,15 +22,9 @@ ENTRY(secondary_trampoline)

>>          * where the physical memory does not start at 0x0.

>>         */

>>  ARM_BE8(setend be)

>> -       adr     r0, 1f

>> -       ldmia   r0, {r1, r2}

>> -       sub     r2, r2, #PAGE_OFFSET

>> +       ldr     r2, =socfpga_cpu1start_addr - PAGE_OFFSET

>

> NAK.  Where do you expect the assembler to place the literal pool for

> this constant?  The only way that'll work is if it's placed before

> "ENTRY(secondary_trampoline_end)" below, but there's no guarantee

> (afaik) where literal pools will be placed.

>


Ah yes, we'd still need to put an .ltorg directive before the end marker.

Alternatively, we could keep the explicit literal but subtract
PAGE_OFFSET there directly (but drop the unused '.' literal and
replace adr+ldmia with ldr)

>>         ldr     r3, [r2]

>>         ldr     r4, [r3]

>>  ARM_BE8(rev    r4, r4)

>>         bx      r4

>> -

>> -       .align

>> -1:     .long   .

>> -       .long   socfpga_cpu1start_addr

>>  ENTRY(secondary_trampoline_end)

>>

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>> linux-arm-kernel@lists.infradead.org

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>

> --

> RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/

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diff mbox

Patch

diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 5d94b7a2fb10..7e4ab55cc529 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,6 +13,7 @@ 
 #include <asm/assembler.h>

        .arch   armv7-a
+       .arm

 ENTRY(secondary_trampoline)
        /* CPU1 will always fetch from 0x0 when it is brought out of reset.
@@ -21,15 +22,9 @@  ENTRY(secondary_trampoline)
         * where the physical memory does not start at 0x0.
        */
 ARM_BE8(setend be)
-       adr     r0, 1f
-       ldmia   r0, {r1, r2}
-       sub     r2, r2, #PAGE_OFFSET
+       ldr     r2, =socfpga_cpu1start_addr - PAGE_OFFSET
        ldr     r3, [r2]
        ldr     r4, [r3]
 ARM_BE8(rev    r4, r4)
        bx      r4
-
-       .align
-1:     .long   .
-       .long   socfpga_cpu1start_addr
 ENTRY(secondary_trampoline_end)