[Linaro-uefi,v3,1/3] Platforms/ARM/Juno: Fix IO window min/max base address in PCIe root complex

Message ID 1461162603-19973-1-git-send-email-sudeep.holla@arm.com
State New
Headers show

Commit Message

Sudeep Holla April 20, 2016, 2:30 p.m.
XPress-RICH3 PCIe driver initializes the root complex with the source
and target address for IO window. The root complex resources in SSDT
should match these settings.

This patch fixes the min/max base address for the IO window in Juno PCIe
root complex ACPI table.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Tomasz Nowicki <tn@semihalf.com>
Cc: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

v2->v3:
	- Fixed $subject and the commit log
v1->v2:
	- Made changes as suggested by Graeme & Tomasz

Patch

diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
index 800d2cb3b2fb..5ff267fe5124 100644
--- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
@@ -107,8 +107,8 @@  DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM
 					PosDecode,
 					EntireRange,
 					0x00000000, 							// Granularity
-					0x5f800000, 							// Min Base Address
-					0x5fffffff, 							// Max Base Address
+					0x00000000, 							// Min Base Address
+					0x000fffff, 							// Max Base Address
 					0x5f800000, 							// Translate
 					0x00800000  							// Length
 				)