diff mbox

[edk2,v4,1/3] Platforms/ARM/Juno: Fix IO window min/max base address in PCIe root complex

Message ID 1461173706-15513-1-git-send-email-sudeep.holla@arm.com
State New
Headers show

Commit Message

Sudeep Holla April 20, 2016, 5:35 p.m. UTC
XPress-RICH3 PCIe driver initializes the root complex with the source
and target address for IO window. The root complex resources in SSDT
should match these settings.

This patch fixes the min/max base address for the IO window in Juno PCIe
root complex ACPI table. It also adds 'TypeTranslation' to the IO window

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Tomasz Nowicki <tn@semihalf.com>
Cc: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

---
 Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

v3->v4:
	- Fixed the max to match the length and added TypeTranslation
v2->v3:
	- Fixed $subject and the commit log
v1->v2:
	- Made changes as suggested by Graeme & Tomasz

-- 
1.9.1

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Comments

Leif Lindholm April 22, 2016, 2:26 p.m. UTC | #1
On Wed, Apr 20, 2016 at 06:35:06PM +0100, Sudeep Holla wrote:
> XPress-RICH3 PCIe driver initializes the root complex with the source

> and target address for IO window. The root complex resources in SSDT

> should match these settings.

> 

> This patch fixes the min/max base address for the IO window in Juno PCIe

> root complex ACPI table. It also adds 'TypeTranslation' to the IO window

> 

> Contributed-under: TianoCore Contribution Agreement 1.0

> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> Cc: Leif Lindholm <leif.lindholm@linaro.org>

> Cc: Tomasz Nowicki <tn@semihalf.com>

> Cc: Graeme Gregory <graeme.gregory@linaro.org>

> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>


Would anyone like to add any ACKs/Reviewed-bys?

> ---

>  Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 7 ++++---

>  1 file changed, 4 insertions(+), 3 deletions(-)

> 

> v3->v4:

> 	- Fixed the max to match the length and added TypeTranslation

> v2->v3:

> 	- Fixed $subject and the commit log

> v1->v2:

> 	- Made changes as suggested by Graeme & Tomasz

> 

> diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

> index 800d2cb3b2fb..969c42398f18 100644

> --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

> +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

> @@ -107,10 +107,11 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM

>  					PosDecode,

>  					EntireRange,

>  					0x00000000, 							// Granularity

> -					0x5f800000, 							// Min Base Address

> -					0x5fffffff, 							// Max Base Address

> +					0x00000000, 							// Min Base Address

> +					0x007fffff, 							// Max Base Address

>  					0x5f800000, 							// Translate

> -					0x00800000  							// Length

> +					0x00800000,  							// Length

> +					,,,TypeTranslation

>  				)

>  			}) // Name(RBUF)

>  

> -- 

> 1.9.1

> 

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Graeme Gregory April 22, 2016, 4:17 p.m. UTC | #2
On 22 April 2016 at 15:26, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Wed, Apr 20, 2016 at 06:35:06PM +0100, Sudeep Holla wrote:

>> XPress-RICH3 PCIe driver initializes the root complex with the source

>> and target address for IO window. The root complex resources in SSDT

>> should match these settings.

>>

>> This patch fixes the min/max base address for the IO window in Juno PCIe

>> root complex ACPI table. It also adds 'TypeTranslation' to the IO window

>>

>> Contributed-under: TianoCore Contribution Agreement 1.0

>> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>> Cc: Leif Lindholm <leif.lindholm@linaro.org>

>> Cc: Tomasz Nowicki <tn@semihalf.com>

>> Cc: Graeme Gregory <graeme.gregory@linaro.org>

>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

>

> Would anyone like to add any ACKs/Reviewed-bys?

>


Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>


Graeme

>> ---

>>  Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 7 ++++---

>>  1 file changed, 4 insertions(+), 3 deletions(-)

>>

>> v3->v4:

>>       - Fixed the max to match the length and added TypeTranslation

>> v2->v3:

>>       - Fixed $subject and the commit log

>> v1->v2:

>>       - Made changes as suggested by Graeme & Tomasz

>>

>> diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

>> index 800d2cb3b2fb..969c42398f18 100644

>> --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

>> +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl

>> @@ -107,10 +107,11 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM

>>                                       PosDecode,

>>                                       EntireRange,

>>                                       0x00000000,                                                     // Granularity

>> -                                     0x5f800000,                                                     // Min Base Address

>> -                                     0x5fffffff,                                                     // Max Base Address

>> +                                     0x00000000,                                                     // Min Base Address

>> +                                     0x007fffff,                                                     // Max Base Address

>>                                       0x5f800000,                                                     // Translate

>> -                                     0x00800000                                                      // Length

>> +                                     0x00800000,                                                     // Length

>> +                                     ,,,TypeTranslation

>>                               )

>>                       }) // Name(RBUF)

>>

>> --

>> 1.9.1

>>

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Leif Lindholm Oct. 26, 2016, 2:49 p.m. UTC | #3
On 22 April 2016 at 17:17, G Gregory <graeme.gregory@linaro.org> wrote:
> On 22 April 2016 at 15:26, Leif Lindholm <leif.lindholm@linaro.org> wrote:

>> On Wed, Apr 20, 2016 at 06:35:06PM +0100, Sudeep Holla wrote:

>>> XPress-RICH3 PCIe driver initializes the root complex with the source

>>> and target address for IO window. The root complex resources in SSDT

>>> should match these settings.

>>>

>>> This patch fixes the min/max base address for the IO window in Juno PCIe

>>> root complex ACPI table. It also adds 'TypeTranslation' to the IO window

>>>

>>> Contributed-under: TianoCore Contribution Agreement 1.0

>>> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>>> Cc: Leif Lindholm <leif.lindholm@linaro.org>

>>> Cc: Tomasz Nowicki <tn@semihalf.com>

>>> Cc: Graeme Gregory <graeme.gregory@linaro.org>

>>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

>>

>> Would anyone like to add any ACKs/Reviewed-bys?

>>

>

> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>


Huh, Jeremy just pointed out that I hadn't pushed this patch.
That has now been addressed - thanks and apologies.

Pushed as fdcd817.
(Subject line slightly trimmed to fit)

Regards,

Leif
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diff mbox

Patch

diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
index 800d2cb3b2fb..969c42398f18 100644
--- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
@@ -107,10 +107,11 @@  DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM
 					PosDecode,
 					EntireRange,
 					0x00000000, 							// Granularity
-					0x5f800000, 							// Min Base Address
-					0x5fffffff, 							// Max Base Address
+					0x00000000, 							// Min Base Address
+					0x007fffff, 							// Max Base Address
 					0x5f800000, 							// Translate
-					0x00800000  							// Length
+					0x00800000,  							// Length
+					,,,TypeTranslation
 				)
 			}) // Name(RBUF)