From patchwork Tue Apr 26 13:03:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 66697 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1598703qge; Tue, 26 Apr 2016 06:03:49 -0700 (PDT) X-Received: by 10.50.220.137 with SMTP id pw9mr19529635igc.65.1461675827846; Tue, 26 Apr 2016 06:03:47 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id k10si3298997igt.72.2016.04.26.06.03.47; Tue, 26 Apr 2016 06:03:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 190B6610F6; Tue, 26 Apr 2016 13:03:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 5D350610B9; Tue, 26 Apr 2016 13:03:45 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6B19E610DE; Tue, 26 Apr 2016 13:03:38 +0000 (UTC) Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by lists.linaro.org (Postfix) with ESMTPS id 8F24D610B9 for ; Tue, 26 Apr 2016 13:03:33 +0000 (UTC) Received: by mail-wm0-f52.google.com with SMTP id e201so111231556wme.0 for ; Tue, 26 Apr 2016 06:03:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=kl/sLDo98ZXpHjsaQwG6Xw8Rmp9k9rmj+3S6/RhCQcc=; b=nJzpmKmrHGqC7nKPD0a5ZWiup4W+IPE+VVxlgy9TEj/XoxefNPgG+iTdZPw9sG1TyX mbtppIoILKtwceQw5iFCUX/5JaiJnNmAJnqruy+Gn5zIT45MwtVxEcUgS6QJKj1iXi4q n9i8SAh8GcyJsHe5Yiv7La2tEPwHyUcGtL8gpfrwsGHDbX9PI7SKK7b5XR2ksBquVZZr OtLnTvLzmCCbvRRHmzJYFUVMVBaHSkY+T4h2ooGilsvdoWzIWfwWY45tjakl7JRUEPJT SoSkYO2IaFPPjYNX+iaBRM9PUBFUeH0QsE5Wcq4i3e7nLqTrlZAbCAMdv0C0IYOnG9RM 2rew== X-Gm-Message-State: AOPr4FVXE9IUORbjIAKDXjOqrEXH286VCO7E2S3PIAfDKqDN1K/kX3tzVCtt2d+TrsX6gVjZDNw= X-Received: by 10.28.41.70 with SMTP id p67mr17963551wmp.70.1461675809783; Tue, 26 Apr 2016 06:03:29 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id u4sm2716840wjz.4.2016.04.26.06.03.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Apr 2016 06:03:28 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, ricardo.salveti@linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org Date: Tue, 26 Apr 2016 15:03:23 +0200 Message-Id: <1461675803-16067-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH] Platforms/Styx: add missing GCD allocation of PCI resources X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The resource apertures that the PCI root bridge uses to assign resources to subordinate devices need to be declared in the GCD memory map before allocations can be made from it. So add the missing code to do that. Also, declare the I/O port space as translated from its CPU visible memory offset, and take the translation into account into the I/O access routines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Note that the 4 GB allocation limit patch is also needed for PCI to work Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++++++++++++++++-- Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 ++ Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 5 +++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 3 ++ 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.c index 66fb27be55ad..99d4203345ba 100644 --- a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -74,7 +74,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = { }; PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1] = { - {{ 0, 255, 0x40000000, 0x20000000, 0xEFFF0000, 0x10000}}, + {{ 0, 255, 0x40000000, 0x41FFFFFFF, 0x0, 0xFFFF, 0xEFFF0000 }}, }; EFI_HANDLE mDriverImageHandle; @@ -124,9 +124,43 @@ InitializePciHostBridge ( UINTN Loop2; PCI_HOST_BRIDGE_INSTANCE *HostBridge; PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - + mDriverImageHandle = ImageHandle; + // + // Add IO and MMIO memory space, so that resources can be allocated in the + // EfiPciHostBridgeAllocateResources phase. + // + Status = gDS->AddIoSpace ( + EfiGcdIoTypeIo, + mResAperture[0][0].IoBase, + mResAperture[0][0].IoLimit - mResAperture[0][0].IoBase + 1 + ); + ASSERT_EFI_ERROR (Status); + + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + mResAperture[0][0].MemBase, + mResAperture[0][0].MemLimit - mResAperture[0][0].MemBase + 1, + EFI_MEMORY_UC + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status)); + return Status; + } + + Status = gDS->SetMemorySpaceAttributes ( + mResAperture[0][0].MemBase, + mResAperture[0][0].MemLimit - mResAperture[0][0].MemBase + 1, + EFI_MEMORY_UC + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__, + Status)); + return Status; + } + + DEBUG((EFI_D_ERROR, "%a () - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR 0x%x\n", __FUNCTION__, sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR))); diff --git a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.h index f91b42a27572..bbd75b20bb47 100644 --- a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -403,6 +403,7 @@ typedef struct { UINT64 IoBase; UINT64 IoLimit; + UINT64 IoTranslation; } PCI_ROOT_BRIDGE_RESOURCE_APERTURE; typedef enum { @@ -455,6 +456,7 @@ typedef struct { UINT64 BusLimit; UINT64 MemLimit; UINT64 IoLimit; + UINT64 IoTranslation; //UINTN PciAddress; //UINTN PciData; diff --git a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 4ac89fb7548f..314a309bb010 100644 --- a/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Platforms/AMD/Styx/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -665,6 +665,7 @@ RootBridgeConstructor ( // PrivateData->MemBase = ResAperture->MemBase; PrivateData->IoBase = ResAperture->IoBase; + PrivateData->IoTranslation = ResAperture->IoTranslation; // // The host bridge only supports 32bit addressing for memory @@ -1005,12 +1006,16 @@ RootBridgeIoIoRW ( UINT8 OutStride; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; UINT8 *Uint8Buffer; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + Address += PrivateData->IoTranslation; + InStride = mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index cd0fe296d849..c1fea8c5361a 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -415,6 +415,9 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + # size of the I/O port space, needed for PCI + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16 + # # ARM Pcds #