From patchwork Wed Apr 27 07:05:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 66771 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2027407qge; Wed, 27 Apr 2016 00:07:27 -0700 (PDT) X-Received: by 10.176.2.179 with SMTP id 48mr3510358uah.122.1461740846070; Wed, 27 Apr 2016 00:07:26 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 94si1595987ual.47.2016.04.27.00.07.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Apr 2016 00:07:26 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1avJXm-0003Tk-04; Wed, 27 Apr 2016 07:05:54 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1avJXk-0003Te-Fr for xen-devel@lists.xen.org; Wed, 27 Apr 2016 07:05:52 +0000 Received: from [85.158.139.211] by server-12.bemta-5.messagelabs.com id CD/01-25799-FC460275; Wed, 27 Apr 2016 07:05:51 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRWlGSWpSXmKPExsVyMfTAet3zKQr hBteLLJZ8XMziwOhxdPdvpgDGKNbMvKT8igTWjDtLfrEVzCmp2NG5nLmBcVFwFyMXh5DAREaJ thv/WEAcFoF2Zolf6yYxgzgSAu9YJG5OWcPUxcgB5MRI/Nrj1sXICWSWS8y82MQMEhYSUJLom FABMegHo8T61WtZQGrYBFQkvr/pZ4WoN5M4f3ImE4gtIiAtce3zZUaQBmaBTkaJnsNnwBqEBS IkFu17wQoylEVAVWLqRS0Qk1fASWJ2HyPEGDmJk8cms05g5F/AyLCKUaM4tagstUjX0EQvqSg zPaMkNzEzR9fQwFQvN7W4ODE9NScxqVgvOT93EyMweBiAYAfj2dOehxglOZiURHmjoxXChfiS 8lMqMxKLM+KLSnNSiw8xanBwCGxeu/oCoxRLXn5eqpIEr1cyUJ1gUWp6akVaZg4wvGFKJTh4l ER4/ROB0rzFBYm5xZnpEKlTjJYcW35fW8vEsWXBDSC5beq9tUxCYPOkxHk9QOYJgDRklObBjY PF4CVGWSlhXkagY4V4ClKLcjNLUOVfMYpzMCoJ85qDTOHJzCuB2/oK6CAmoIMuH5IFOagkESE l1cDIfEz68S8fTgaVnPqf0jdaXx14oLOt4/806/a5JT+Xb3+RnPNR611Sgd6txVOkHGx66mbv 2Hrd0sqWu57/1zX+WR2+mbem2q9IMYitzcxcdFnH5Kz9s8RN73++P7zZbGoJ59Fve5dKcjE9X bc85JPUXK6PP9ek2NeerDt4lvXK0opZ3/cq1mlLKLEUZyQaajEXFScCADLZWcO8AgAA X-Env-Sender: wei.chen@linaro.org X-Msg-Ref: server-2.tower-206.messagelabs.com!1461740749!20587763!1 X-Originating-IP: [209.85.192.175] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24354 invoked from network); 27 Apr 2016 07:05:50 -0000 Received: from mail-pf0-f175.google.com (HELO mail-pf0-f175.google.com) (209.85.192.175) by server-2.tower-206.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 27 Apr 2016 07:05:50 -0000 Received: by mail-pf0-f175.google.com with SMTP id n1so18616558pfn.2 for ; Wed, 27 Apr 2016 00:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=OsAeNzvRgX395Zrjrvoci3j6O29cm7DTUsPZK0CTpUY=; b=ahKkZj59hdeZJ6xTlca9XD29JCReoyc7W+iEHm8XjxaeFBa613WZ58Oyx4l/V8yxQp 2SEJXCSptesfvaFs5/1AWg8i+rtVNDVMv7+GRcWuZbt/bvsNuR1MXEXBOLPSXc9t4xz9 T7sp/YBaeGZOEI7OW19/LI3ed+vj8BLzUPlN4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=OsAeNzvRgX395Zrjrvoci3j6O29cm7DTUsPZK0CTpUY=; b=F+K/esmF/HT923qX8XZWHNa5+6wl67bU6el/pOooEavSe+51xLBzfpTR6oGEcCHVe5 EyceNHX5qNwfE9UY7O1Hx00x9OClKUtDeI/3W2eFk2W5vbO4vg/YcGVPiGObXldX8yII YzB9IkOqV0u1eZ2z/8q2cToUuqmRhQdyj1xZgsUvfWyvwFaIb0odfpM57JmcEibmeRzB 4aTAtz80r6oIYs/2w/wgmqmEsTXBK7nhG6tmEZ8E/mqenSlkSQWGgoPsnuwaW5s21u8P UHuziPTTzS2LUR3SKYfnob0rVCu7VVRemGq25+ZLC+XMbGLkQrI1cGZOjdZZ4bAXQcWe HNsg== X-Gm-Message-State: AOPr4FU8qABdKyZZ+rX0ikOcmWE/uTcdqIHeV9S3yQoMkf4sQDf59Z1U7Xm2HSp/NY92rpVS X-Received: by 10.98.44.72 with SMTP id s69mr9529883pfs.31.1461740749386; Wed, 27 Apr 2016 00:05:49 -0700 (PDT) Received: from li713-35.members.linode.com ([2400:8900::f03c:91ff:fe56:1324]) by smtp.gmail.com with ESMTPSA id dh4sm3693053pad.37.2016.04.27.00.05.47 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 27 Apr 2016 00:05:48 -0700 (PDT) From: Wei Chen X-Google-Original-From: Wei Chen To: xen-devel@lists.xen.org Date: Wed, 27 Apr 2016 15:05:43 +0800 Message-Id: <1461740743-2459-1-git-send-email-Wei.Chen@linaro.org> X-Mailer: git-send-email 1.9.1 Cc: julien.grall@arm.com, sstabellini@kernel.org, Wei Chen , suravee.suthikulpanit@amd.com, steve.capper@arm.com Subject: [Xen-devel] [PATCH v3] xen/arm: gicv2: Export GICv2m register frames to Dom0 by device tree X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" This patch adds v2m extension support in GIC-v2 driver. The GICv2 driver detects the MSI frames from device tree and creates corresponding device tree nodes in dom0's DTB. It also provides one hw_ops callback to map v2m MMIO regions to dom0 and route v2m SPIs to dom0. With this GICv2m extension support, the dom0 kernel can do GICv2m frame setup and initialization. This patch is based on the GICv2m patch of Suravee Suthikulpanit: [PATCH 2/2] xen/arm: gicv2: Adding support for GICv2m in Dom0 http://lists.xen.org/archives/html/xen-devel/2015-04/msg02613.html Signed-off-by: Wei Chen Reviewed-by: Julien Grall --- v3: Address comments from Julien 1. Add missed non-DT code to the separate function. 2. Fix some typos 3. Fix indentation issues. v2: Address comments from Julien 1. Pull non-DT code in a separate function. 2. Fix one variable type error. 3. Fix indentation issues. 4. Revise some code comments. xen/arch/arm/domain_build.c | 5 + xen/arch/arm/gic-v2.c | 298 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 9 ++ xen/include/asm-arm/gic.h | 3 + 4 files changed, 315 insertions(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 00dc07a..2e4c295 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2177,6 +2177,11 @@ int construct_dom0(struct domain *d) if ( rc < 0 ) return rc; + /* Map extra GIC MMIO, irqs and other hw stuffs to dom0. */ + rc = gic_map_hwdom_extra_mappings(d); + if ( rc < 0 ) + return rc; + rc = platform_specific_mapping(d); if ( rc < 0 ) return rc; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 450755f..afeab57 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,41 @@ #define GICH_V2_VMCR_PRIORITY_MASK 0x1f #define GICH_V2_VMCR_PRIORITY_SHIFT 27 +/* GICv2m extension register definitions. */ +/* +* MSI_TYPER: +* [31:26] Reserved +* [25:16] lowest SPI assigned to MSI +* [15:10] Reserved +* [9:0] Number of SPIs assigned to MSI +*/ +#define V2M_MSI_TYPER 0x008 +#define V2M_MSI_TYPER_BASE_SHIFT 16 +#define V2M_MSI_TYPER_BASE_MASK 0x3FF +#define V2M_MSI_TYPER_NUM_MASK 0x3FF +#define V2M_MSI_SETSPI_NS 0x040 +#define V2M_MIN_SPI 32 +#define V2M_MAX_SPI 1019 +#define V2M_MSI_IIDR 0xFCC + +#define V2M_MSI_TYPER_BASE_SPI(x) \ + (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK) + +#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK) + +struct v2m_data { + struct list_head entry; + /* Pointer to the DT node representing the v2m frame */ + const struct dt_device_node *dt_node; + paddr_t addr; /* Register frame base */ + paddr_t size; /* Register frame size */ + u32 spi_start; /* The SPI number that MSIs start */ + u32 nr_spis; /* The number of SPIs for MSIs */ +}; + +/* v2m extension register frame information list */ +static LIST_HEAD(gicv2m_info); + /* Global state */ static struct { void __iomem * map_dbase; /* IO mapped Address of distributor registers */ @@ -551,6 +587,167 @@ static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_m spin_unlock(&gicv2.lock); } +static int gicv2_map_hwdown_extra_mappings(struct domain *d) +{ + const struct v2m_data *v2m_data; + + /* For the moment, we'll assign all v2m frames to the hardware domain. */ + list_for_each_entry( v2m_data, &gicv2m_info, entry ) + { + int ret; + u32 spi; + + printk("GICv2: Mapping v2m frame to d%d: addr=0x%lx size=0x%lx spi_base=%u num_spis=%u\n", + d->domain_id, v2m_data->addr, v2m_data->size, + v2m_data->spi_start, v2m_data->nr_spis); + + ret = map_mmio_regions(d, paddr_to_pfn(v2m_data->addr), + DIV_ROUND_UP(v2m_data->size, PAGE_SIZE), + paddr_to_pfn(v2m_data->addr)); + if ( ret ) + { + printk(XENLOG_ERR "GICv2: Map v2m frame to d%d failed.\n", + d->domain_id); + return ret; + } + + /* + * Map all SPIs that are allocated to MSIs for the frame to the + * domain. + */ + for ( spi = v2m_data->spi_start; + spi < (v2m_data->spi_start + v2m_data->nr_spis); spi++ ) + { + /* + * MSIs are always edge-triggered. Configure the associated SPIs + * to be edge-rising as default type. + */ + ret = irq_set_spi_type(spi, IRQ_TYPE_EDGE_RISING); + if ( ret ) + { + printk(XENLOG_ERR + "GICv2: Failed to set v2m MSI SPI[%d] type.\n", spi); + return ret; + } + + /* Route a SPI that is allocated to MSI to the domain. */ + ret = route_irq_to_guest(d, spi, spi, "v2m"); + if ( ret ) + { + printk(XENLOG_ERR + "GICv2: Failed to route v2m MSI SPI[%d] to Dom%d.\n", + spi, d->domain_id); + return ret; + } + + /* Reserve a SPI that is allocated to MSI for the domain. */ + if ( !vgic_reserve_virq(d, spi) ) + { + printk(XENLOG_ERR + "GICv2: Failed to reserve v2m MSI SPI[%d] for Dom%d.\n", + spi, d->domain_id); + return -EINVAL; + } + } + } + + return 0; +} + +/* + * Set up gic v2m DT sub-node. + * Please refer to the binding document: + * https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt + */ +static int gicv2m_make_dt_node(const struct domain *d, + const struct dt_device_node *gic, + void *fdt) +{ + u32 len; + int res; + const void *prop = NULL; + const struct dt_device_node *v2m = NULL; + const struct v2m_data *v2m_data; + + /* The sub-nodes require the ranges property */ + prop = dt_get_property(gic, "ranges", &len); + if ( !prop ) + { + printk(XENLOG_ERR "Can't find ranges property for the gic node\n"); + return -FDT_ERR_XEN(ENOENT); + } + + res = fdt_property(fdt, "ranges", prop, len); + if ( res ) + return res; + + list_for_each_entry( v2m_data, &gicv2m_info, entry ) + { + v2m = v2m_data->dt_node; + + printk("GICv2: Creating v2m DT node for d%d: addr=0x%lx size=0x%lx spi_base=%u num_spis=%u\n", + d->domain_id, v2m_data->addr, v2m_data->size, + v2m_data->spi_start, v2m_data->nr_spis); + + res = fdt_begin_node(fdt, v2m->name); + if ( res ) + return res; + + res = fdt_property_string(fdt, "compatible", "arm,gic-v2m-frame"); + if ( res ) + return res; + + res = fdt_property(fdt, "msi-controller", NULL, 0); + if ( res ) + return res; + + if ( v2m->phandle ) + { + res = fdt_property_cell(fdt, "phandle", v2m->phandle); + if ( res ) + return res; + } + + /* Use the same reg regions as v2m node in host DTB. */ + prop = dt_get_property(v2m, "reg", &len); + if ( !prop ) + { + printk(XENLOG_ERR "GICv2: Can't find v2m reg property.\n"); + res = -FDT_ERR_XEN(ENOENT); + return res; + } + + res = fdt_property(fdt, "reg", prop, len); + if ( res ) + return res; + + /* + * The properties msi-base-spi and msi-num-spis are used to override + * the hardware settings. Therefore it is fine to always write them + * in the guest DT. + */ + res = fdt_property_u32(fdt, "arm,msi-base-spi", v2m_data->spi_start); + if ( res ) + { + printk(XENLOG_ERR + "GICv2: Failed to create v2m msi-base-spi in Guest DT.\n"); + return res; + } + + res = fdt_property_u32(fdt, "arm,msi-num-spis", v2m_data->nr_spis); + if ( res ) + { + printk(XENLOG_ERR + "GICv2: Failed to create v2m msi-num-spis in Guest DT.\n"); + return res; + } + + fdt_end_node(fdt); + } + + return res; +} + static int gicv2_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, void *fdt) @@ -587,6 +784,10 @@ static int gicv2_make_hwdom_dt_node(const struct domain *d, len *= 2; res = fdt_property(fdt, "reg", regs, len); + if ( res ) + return res; + + res = gicv2m_make_dt_node(d, gic, fdt); return res; } @@ -632,6 +833,96 @@ static bool_t gicv2_is_aliased(paddr_t cbase, paddr_t csize) return ((val_low & 0xfff0fff) == 0x0202043B && val_low == val_high); } +static void gicv2_add_v2m_frame_to_list(paddr_t addr, paddr_t size, + u32 spi_start, u32 nr_spis, + const struct dt_device_node *v2m) +{ + struct v2m_data *v2m_data; + + /* + * If the hardware setting hasn't been overridden by DT or ACPI, we have + * to read base_spi and num_spis from hardware registers to reserve irqs. + */ + if ( !spi_start || !nr_spis ) + { + u32 msi_typer; + void __iomem *base; + + base = ioremap_nocache(addr, size); + if ( !base ) + panic("GICv2: Cannot remap v2m register frame"); + + msi_typer = readl_relaxed(base + V2M_MSI_TYPER); + spi_start = V2M_MSI_TYPER_BASE_SPI(msi_typer); + nr_spis = V2M_MSI_TYPER_NUM_SPI(msi_typer); + + iounmap(base); + } + + if ( spi_start < V2M_MIN_SPI ) + panic("GICv2: Invalid v2m base SPI:%u\n", spi_start); + + if ( ( nr_spis == 0 ) || ( spi_start + nr_spis > V2M_MAX_SPI ) ) + panic("GICv2: Number of v2m SPIs (%u) exceed maximum (%u)\n", + nr_spis, V2M_MAX_SPI - V2M_MIN_SPI + 1); + + /* Allocate an entry to record new v2m frame information. */ + v2m_data = xzalloc_bytes(sizeof(struct v2m_data)); + if ( !v2m_data ) + panic("GICv2: Cannot allocate memory for v2m frame"); + + INIT_LIST_HEAD(&v2m_data->entry); + v2m_data->addr = addr; + v2m_data->size = size; + v2m_data->spi_start = spi_start; + v2m_data->nr_spis = nr_spis; + v2m_data->dt_node = v2m; + + printk("GICv2m extension register frame:\n" + " gic_v2m_addr=%"PRIpaddr"\n" + " gic_v2m_size=%"PRIpaddr"\n" + " gic_v2m_spi_base=%u\n" + " gic_v2m_num_spis=%u\n", + v2m_data->addr, v2m_data->size, + v2m_data->spi_start, v2m_data->nr_spis); + + list_add_tail(&v2m_data->entry, &gicv2m_info); +} + +static void gicv2_extension_dt_init(const struct dt_device_node *node) +{ + const struct dt_device_node *v2m = NULL; + + /* + * Check whether this GIC implements the v2m extension. If so, + * add v2m register frames to gicv2m_info. + */ + dt_for_each_child_node(node, v2m) + { + u32 spi_start = 0, nr_spis = 0; + paddr_t addr, size; + + if ( !dt_device_is_compatible(v2m, "arm,gic-v2m-frame") ) + continue; + + /* Get register frame resource from DT. */ + if ( dt_device_get_address(v2m, 0, &addr, &size) ) + panic("GICv2: Cannot find a valid v2m frame address"); + + /* + * Check whether DT uses msi-base-spi and msi-num-spis properties to + * override the hardware setting. + */ + if ( dt_property_read_u32(v2m, "arm,msi-base-spi", &spi_start) && + dt_property_read_u32(v2m, "arm,msi-num-spis", &nr_spis) ) + printk("GICv2: DT overriding v2m hardware setting (base:%u, num:%u)\n", + spi_start, nr_spis); + + /* Add this v2m frame information to list. */ + gicv2_add_v2m_frame_to_list(addr, size, spi_start, nr_spis, v2m); + } +} + static paddr_t __initdata hbase, dbase, cbase, csize, vbase; static void __init gicv2_dt_init(void) @@ -683,6 +974,12 @@ static void __init gicv2_dt_init(void) if ( csize != vsize ) panic("GICv2: Sizes of GICC (%#"PRIpaddr") and GICV (%#"PRIpaddr") don't match\n", csize, vsize); + + /* + * Check whether this GIC implements the v2m extension. If so, + * add v2m register frames to gicv2_extension_info. + */ + gicv2_extension_dt_init(node); } static int gicv2_iomem_deny_access(const struct domain *d) @@ -936,6 +1233,7 @@ const static struct gic_hw_operations gicv2_ops = { .read_apr = gicv2_read_apr, .make_hwdom_dt_node = gicv2_make_hwdom_dt_node, .make_hwdom_madt = gicv2_make_hwdom_madt, + .map_hwdom_extra_mappings = gicv2_map_hwdown_extra_mappings, .iomem_deny_access = gicv2_iomem_deny_access, }; diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 2bfe4de..12bb0ab 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -230,6 +230,15 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, return 0; } +/* Map extra GIC MMIO, irqs and other hw stuffs to the hardware domain. */ +int gic_map_hwdom_extra_mappings(struct domain *d) +{ + if ( gic_hw_ops->map_hwdom_extra_mappings ) + return gic_hw_ops->map_hwdom_extra_mappings(d); + + return 0; +} + static void __init gic_dt_preinit(void) { int rc; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index cd97bb2..836f1ad 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -360,6 +360,8 @@ struct gic_hw_operations { const struct dt_device_node *gic, void *fdt); /* Create MADT table for the hardware domain */ int (*make_hwdom_madt)(const struct domain *d, u32 offset); + /* Map extra GIC MMIO, irqs and other hw stuffs to the hardware domain. */ + int (*map_hwdom_extra_mappings)(struct domain *d); /* Deny access to GIC regions */ int (*iomem_deny_access)(const struct domain *d); }; @@ -369,6 +371,7 @@ int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, void *fdt); int gic_make_hwdom_madt(const struct domain *d, u32 offset); +int gic_map_hwdom_extra_mappings(struct domain *d); int gic_iomem_deny_access(const struct domain *d); #endif /* __ASSEMBLY__ */