From patchwork Wed Apr 27 13:16:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 66792 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2183806qge; Wed, 27 Apr 2016 06:17:29 -0700 (PDT) X-Received: by 10.107.17.151 with SMTP id 23mr10028338ior.101.1461763049005; Wed, 27 Apr 2016 06:17:29 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id y17si19055408igg.35.2016.04.27.06.17.28; Wed, 27 Apr 2016 06:17:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 87B5F610DE; Wed, 27 Apr 2016 13:17:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 9FF00610D4; Wed, 27 Apr 2016 13:17:07 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id CCA2A6044B; Wed, 27 Apr 2016 13:16:59 +0000 (UTC) Received: from mail-wm0-f42.google.com (mail-wm0-f42.google.com [74.125.82.42]) by lists.linaro.org (Postfix) with ESMTPS id 8ABBB6044B for ; Wed, 27 Apr 2016 13:16:56 +0000 (UTC) Received: by mail-wm0-f42.google.com with SMTP id n129so26993502wmn.1 for ; Wed, 27 Apr 2016 06:16:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4fQytxZvhwjKPutSoPxULL+Eam04UxRJ1CiZ0+Zd3v0=; b=BGi1c+tSWLFTOxg1VQqsZ0Ndrwrnwc1zwRLBPcb2SW6O3kYrL7FaskV2AJkWH6l7FT gupeNW7TkdDywv+uwviIsTgv7ybA2+i/AaGbGcSucQV9EJV4U/5J6O8E4zYsU3uv0DyM Zjbg88LijZg6kCsPNbYMrgBb3whJnHUfU0/SITXvm3m6q6n6/7NuM2q4SzKDtSX+bWUh OMVwPMs0Pb0dVxiHyfw6DA67kLj9LcoPHC3CHi4bFXKDfO2x/e4sfpmVT4uhbKk3q+Ul bNn51PQcaTEZDhXpxC4LNTqOXqf6+pEYCZ/3KT5tmTSQwfq1eah+F/o3YyYLq/PSzNFl HgEw== X-Gm-Message-State: AOPr4FUr4AgMb1ZTxbDJA0OoVWchYPxi9bzFf/O2+vMyiX+0k8Ts/gt8b8uY/cso2LqjNy30AlI= X-Received: by 10.28.144.20 with SMTP id s20mr10410452wmd.12.1461763015672; Wed, 27 Apr 2016 06:16:55 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id w77sm29244897wmw.10.2016.04.27.06.16.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Apr 2016 06:16:54 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, ricardo.salveti@linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org Date: Wed, 27 Apr 2016 15:16:48 +0200 Message-Id: <1461763009-23741-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1461763009-23741-1-git-send-email-ard.biesheuvel@linaro.org> References: <1461763009-23741-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 1/2] Platforms/AMD/Styx: implement PciHostBridgeLib X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" In preparation of moving to the generic implementation of PciHostBridgeDxe, supply an implementation of PciHostBridgeLib that encapsulates the platform specific parameters that describe the PCI host bridge. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc | 15 ++ Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c | 196 ++++++++++++++++++++ Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf | 55 ++++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 15 ++ 4 files changed, 281 insertions(+) diff --git a/Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc b/Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc index 599e259c464f..c863413519a0 100644 --- a/Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc +++ b/Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc @@ -476,6 +476,21 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # PCIe Support gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 + gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0 + gArmPlatformTokenSpaceGuid.PcdPciBusMax|0xFF + + gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0 + gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x10000 + gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0xBFFF0000 + + gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x40000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x7FFF0000 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0 + + gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x100000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0 + ## Use PCI emulation for ATA PassThru gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c new file mode 100644 index 000000000000..1bdb0025dee4 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -0,0 +1,196 @@ +/** @file + PCI Host Bridge Library instance for AMD Seattle SOC + + Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include +#include + +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A08), // PCI Express + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + PCI_ROOT_BRIDGE *RootBridge; + + *Count = 1; + RootBridge = AllocateZeroPool (*Count * sizeof *RootBridge); + + RootBridge->Segment = 0; + + RootBridge->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_MEMORY | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + RootBridge->Attributes = RootBridge->Supports; + + RootBridge->DmaAbove4G = TRUE; + + RootBridge->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | + EFI_PCI_HOST_BRIDGE_MEM64_DECODE ; + + RootBridge->Bus.Base = PcdGet32 (PcdPciBusMin); + RootBridge->Bus.Limit = PcdGet32 (PcdPciBusMax); + RootBridge->Io.Base = PcdGet64 (PcdPciIoBase); + RootBridge->Io.Limit = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1; + RootBridge->Mem.Base = PcdGet32 (PcdPciMmio32Base); + RootBridge->Mem.Limit = PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1; + RootBridge->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base); + RootBridge->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1; + + // + // No separate ranges for prefetchable and non-prefetchable BARs + // + RootBridge->PMem.Base = 0; + RootBridge->PMem.Limit = 0; + RootBridge->PMemAbove4G.Base = 0; + RootBridge->PMemAbove4G.Limit = 0; + + ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0); + ASSERT (FixedPcdGet64 (PcdPciMmio64Translation) == 0); + + RootBridge->NoExtendedConfigSpace = FALSE; + + RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath; + + return RootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + FreePool (Bridges); +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf new file mode 100644 index 000000000000..d73017c00b48 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf @@ -0,0 +1,55 @@ +## @file +# PCI Host Bridge Library instance for AMD Seattle SOC +# +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmdStyxPciHostBridgeLib + FILE_GUID = 05E7AB83-EF8D-482D-80F8-905B73377A15 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + AmdStyxPciHostBridgeLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdPciBusMin + gArmPlatformTokenSpaceGuid.PcdPciBusMax + gArmPlatformTokenSpaceGuid.PcdPciIoBase + gArmPlatformTokenSpaceGuid.PcdPciIoSize + gArmPlatformTokenSpaceGuid.PcdPciMmio32Base + gArmPlatformTokenSpaceGuid.PcdPciMmio32Size + gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation + gArmPlatformTokenSpaceGuid.PcdPciMmio64Base + gArmPlatformTokenSpaceGuid.PcdPciMmio64Size + gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index cd0fe296d849..eb8c9a4e27ee 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -477,6 +477,21 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # PCIe Support gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 + gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0 + gArmPlatformTokenSpaceGuid.PcdPciBusMax|0xFF + + gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0 + gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x10000 + gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0xBFFF0000 + + gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x40000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x7FFF0000 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0 + + gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x100000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0 + ## Use PCI emulation for ATA PassThru gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE