From patchwork Thu Apr 28 08:15:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Auger Eric X-Patchwork-Id: 66861 Delivered-To: patches@linaro.org Received: by 10.140.93.198 with SMTP id d64csp75510qge; Thu, 28 Apr 2016 01:15:40 -0700 (PDT) X-Received: by 10.28.165.209 with SMTP id o200mr28628548wme.61.1461831339017; Thu, 28 Apr 2016 01:15:39 -0700 (PDT) Return-Path: Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com. [2a00:1450:400c:c09::230]) by mx.google.com with ESMTPS id h3si9312560wjp.176.2016.04.28.01.15.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Apr 2016 01:15:39 -0700 (PDT) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::230 as permitted sender) client-ip=2a00:1450:400c:c09::230; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::230 as permitted sender) smtp.mailfrom=eric.auger@linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by mail-wm0-x230.google.com with SMTP id a17so51624352wme.0 for ; Thu, 28 Apr 2016 01:15:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=09N64aywEGNO0fhwQxQi7W/5ig3IHTDF3eT1pmu/nCo=; b=MY/WlclUVj7guNDi0v5v05q1/5PHsQYwGdzG7Dz2kbWJU+1+Ijdhk3uRYmHy2I2Q4O 6Rtw1pvHrnouX9OxNv3Fz4GR/h9Zjm5YRt6ho8csv0KA0vYzXuMjPN+TNcapqeWG1bv3 VO/BkyHrGEsL7WDnwqhMPVmY245lQ8vS9tn4U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=09N64aywEGNO0fhwQxQi7W/5ig3IHTDF3eT1pmu/nCo=; b=JZ8EW5p1uh+kcM40BeHEPm229L+VVtRnv6uqWGK7FGZe86FU8uBThIkHww5BP2k9XV nbi2MwbPswuWPdX3K5JwIoKzduia3dpJE3cI7ry9by4/WlBgdKA91JzWjptwo6TXqzj9 GleBWKGbiMN9mNVibjol/J+QbbOn3HXUjHyjI+pgw8tTD3aUVj6ibmaGJD1MTcYR1KDS Sk1VEF5dbhf4vHUcQQ1EkOUaRt0aD7kcz1n6B/6D2nOP2/ZKkoK9tgueMaGRujp7cn5Y oJbnmagCqL/QxYRbdsazjSMNul6mJip7F6G1lokdV09l3gKuIoR3g35LKyzDc2KVan+9 Ihrw== X-Gm-Message-State: AOPr4FXBBfcO76IT2RzCPb40F9B7iV24DR+jLyo82u787upsiakT2e8WUxgIcuok4vlSO5fQP8A= X-Received: by 10.28.174.70 with SMTP id x67mr14047786wme.43.1461831338793; Thu, 28 Apr 2016 01:15:38 -0700 (PDT) Return-Path: Received: from new-host-46.home (LMontsouris-657-1-37-90.w80-11.abo.wanadoo.fr. [80.11.198.90]) by smtp.gmail.com with ESMTPSA id h8sm12749860wmd.2.2016.04.28.01.15.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Apr 2016 01:15:37 -0700 (PDT) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, robin.murphy@arm.com, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, linux-kernel@vger.kernel.org, Bharat.Bhushan@freescale.com, pranav.sawargaonkar@gmail.com, p.fedin@samsung.com, iommu@lists.linux-foundation.org, Jean-Philippe.Brucker@arm.com, julien.grall@arm.com Subject: [PATCH v8 3/8] iommu: introduce an msi cookie Date: Thu, 28 Apr 2016 08:15:18 +0000 Message-Id: <1461831323-5480-4-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461831323-5480-1-git-send-email-eric.auger@linaro.org> References: <1461831323-5480-1-git-send-email-eric.auger@linaro.org> This opaque pointer will enable to store information about msi iommu mappings. Signed-off-by: Eric Auger --- v7 -> v8: remove spinlock and RB tree v5 -> v6: - initialize reserved_binding_list - use a spinlock instead of a mutex --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ea5d288..cb8d30a 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -91,6 +91,7 @@ struct iommu_domain { struct iommu_domain_geometry geometry; struct iommu_domain_msi_geometry msi_geometry; void *iova_cookie; + void *msi_cookie; }; enum iommu_cap {