[Linaro-uefi] Override PrePeiCoreMPCore to allow 64-bit mailbox pointers

Message ID 1461973244-5072-1-git-send-email-leo.duran@amd.com
State New
Headers show

Commit Message

Duran, Leo April 29, 2016, 11:40 p.m.
This patch supersedes PATCH 4/4 of the previous series.
The path to the Override files is now correct.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
 .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc     |   2 +-
 .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf     |   2 +-
 .../PrePeiCore/AArch64/ArchPrePeiCore.c            |  58 +++++++
 .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S  | 126 ++++++++++++++++
 .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S     |  54 +++++++
 .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S      | 112 ++++++++++++++
 .../PrePeiCore/AArch64/SwitchStack.S               |  49 ++++++
 .../ArmPlatformPkg/PrePeiCore/MainMPCore.c         | 168 +++++++++++++++++++++
 .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c         | 149 ++++++++++++++++++
 .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h         |  85 +++++++++++
 .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf |  76 ++++++++++
 11 files changed, 879 insertions(+), 2 deletions(-)
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
 create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

Comments

Ard Biesheuvel May 1, 2016, 8:08 a.m. | #1
On 30 April 2016 at 01:40, Leo Duran <leo.duran@amd.com> wrote:
> This patch supersedes PATCH 4/4 of the previous series.
> The path to the Override files is now correct.
>

Actually, after thinking about this a bit more, I think it is not
Overdrive that needs the override but VExpress. I will propose patches
to make FVP and Juno PSCI only, allowing us to turn the current MPCore
implementation into a 32-bit VExpress specific one. Next, I will
propose a new implementation that more closely resembles what we need
to do to implement the ACPI parking protocol (i.e., 1 reserved page
per core, etc etc), which should support Overdrive in non-PSCI mode
but also other implementations like Xgene which boots in EL2


> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
>  .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc     |   2 +-
>  .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf     |   2 +-
>  .../PrePeiCore/AArch64/ArchPrePeiCore.c            |  58 +++++++
>  .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S  | 126 ++++++++++++++++
>  .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S     |  54 +++++++
>  .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S      | 112 ++++++++++++++
>  .../PrePeiCore/AArch64/SwitchStack.S               |  49 ++++++
>  .../ArmPlatformPkg/PrePeiCore/MainMPCore.c         | 168 +++++++++++++++++++++
>  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c         | 149 ++++++++++++++++++
>  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h         |  85 +++++++++++
>  .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf |  76 ++++++++++
>  11 files changed, 879 insertions(+), 2 deletions(-)
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
>  create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
>
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> index e83a8ef..6ee7181 100644
> --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> @@ -561,7 +561,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2)
>  !if $(DO_PSCI)
>    ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
>  !else
> -  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> +  OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
>  !endif
>    MdeModulePkg/Core/Pei/PeiMain.inf
>    MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
> index cbfb6c3..0134af2 100644
> --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
> +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
> @@ -250,7 +250,7 @@ READ_LOCK_STATUS   = TRUE
>  !if $(DO_PSCI)
>    INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
>  !else
> -  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> +  INF OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
>  !endif
>    INF MdeModulePkg/Core/Pei/PeiMain.inf
>    INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
> new file mode 100644
> index 0000000..9f86d3e
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
> @@ -0,0 +1,58 @@
> +/** @file
> +*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
> +*
> +*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +*  Copyright (c) 2016, AMD Inc. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +/**
> +  Unmodified from:
> +   ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
> +
> +**/
> +
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "PrePeiCore.h"
> +
> +VOID
> +PeiCommonExceptionEntry (
> +  IN UINT32 Entry,
> +  IN UINTN LR
> +  )
> +{
> +  CHAR8           Buffer[100];
> +  UINTN           CharCount;
> +
> +  switch (Entry) {
> +  case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:
> +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR);
> +    break;
> +  case EXCEPT_AARCH64_IRQ:
> +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR);
> +    break;
> +  case EXCEPT_AARCH64_FIQ:
> +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR);
> +    break;
> +  case EXCEPT_AARCH64_SERROR:
> +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR);
> +    break;
> +  default:
> +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR);
> +    break;
> +  }
> +
> +  SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> +  while(1);
> +}
> +
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
> new file mode 100644
> index 0000000..38a4257
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
> @@ -0,0 +1,126 @@
> +#
> +#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +#  Copyright (c) 2016, AMD Inc. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +#/**
> +#  Unmodified from:
> +#   ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
> +#
> +#**/
> +
> +#include <Chipset/AArch64.h>
> +#include <AsmMacroIoLibV8.h>
> +#include <Base.h>
> +#include <AutoGen.h>
> +
> +.text
> +
> +//============================================================
> +//Default Exception Handlers
> +//============================================================
> +
> +#define TO_HANDLER                                              \
> +   EL1_OR_EL2(x1)                                               \
> +1: mrs  x1, elr_el1    /* EL1 Exception Link Register */       ;\
> +   b    3f                                                     ;\
> +2: mrs  x1, elr_el2    /* EL2 Exception Link Register */       ;\
> +3: bl   ASM_PFX(PeiCommonExceptionEntry)                       ;
> +
> +
> +//
> +// Default Exception handlers: There is no plan to return from any of these exceptions.
> +// No context saving at all.
> +//
> +
> +VECTOR_BASE(PeiVectorTable)
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
> +_DefaultSyncExceptHandler_t:
> +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
> +_DefaultIrq_t:
> +  mov  x0, #EXCEPT_AARCH64_IRQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
> +_DefaultFiq_t:
> +  mov  x0, #EXCEPT_AARCH64_FIQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
> +_DefaultSError_t:
> +  mov  x0, #EXCEPT_AARCH64_SERROR
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
> +_DefaultSyncExceptHandler_h:
> +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
> +_DefaultIrq_h:
> +  mov  x0, #EXCEPT_AARCH64_IRQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
> +_DefaultFiq_h:
> +  mov  x0, #EXCEPT_AARCH64_FIQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
> +_DefaultSError_h:
> +  mov  x0, #EXCEPT_AARCH64_SERROR
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
> +_DefaultSyncExceptHandler_LowerA64:
> +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
> +_DefaultIrq_LowerA64:
> +  mov  x0, #EXCEPT_AARCH64_IRQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
> +_DefaultFiq_LowerA64:
> +  mov  x0, #EXCEPT_AARCH64_FIQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
> +_DefaultSError_LowerA64:
> +  mov  x0, #EXCEPT_AARCH64_SERROR
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
> +_DefaultSyncExceptHandler_LowerA32:
> +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
> +_DefaultIrq_LowerA32:
> +  mov  x0, #EXCEPT_AARCH64_IRQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
> +_DefaultFiq_LowerA32:
> +  mov  x0, #EXCEPT_AARCH64_FIQ
> +  TO_HANDLER
> +
> +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
> +_DefaultSError_LowerA32:
> +  mov  x0, #EXCEPT_AARCH64_SERROR
> +  TO_HANDLER
> +
> +VECTOR_END(PeiVectorTable)
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
> new file mode 100644
> index 0000000..b9a0049
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
> @@ -0,0 +1,54 @@
> +#========================================================================================
> +#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +#  Copyright (c) 2016, AMD Inc. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http:#opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#=======================================================================================
> +#/**
> +#  Unmodified from:
> +#   ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
> +#
> +#**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Chipset/AArch64.h>
> +
> +#start of the code section
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(SetupExceptionLevel1)
> +GCC_ASM_EXPORT(SetupExceptionLevel2)
> +
> +// Setup EL1 while in EL1
> +ASM_PFX(SetupExceptionLevel1):
> +   mov  x5, x30                   // Save LR
> +
> +   mov  x0, #CPACR_CP_FULL_ACCESS
> +   bl   ASM_PFX(ArmWriteCpacr)    // Disable copro traps to EL1
> +
> +   ret  x5
> +
> +// Setup EL2 while in EL2
> +ASM_PFX(SetupExceptionLevel2):
> +   msr     sctlr_el2, xzr
> +   mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register
> +
> +   // Send all interrupts to their respective Exception levels for EL2
> +   orr     x0, x0, #(1 << 3)      // Enable EL2 FIQ
> +   orr     x0, x0, #(1 << 4)      // Enable EL2 IRQ
> +   orr     x0, x0, #(1 << 5)      // Enable EL2 SError and Abort
> +   msr     hcr_el2, x0            // Write back our settings
> +
> +   msr     cptr_el2, xzr          // Disable copro traps to EL2
> +
> +   ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
> new file mode 100644
> index 0000000..2ddf4d4
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
> @@ -0,0 +1,112 @@
> +//
> +//  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +//  Copyright (c) 2016, AMD Inc. All rights reserved.
> +//
> +//  This program and the accompanying materials
> +//  are licensed and made available under the terms and conditions of the BSD License
> +//  which accompanies this distribution.  The full text of the license may be found at
> +//  http://opensource.org/licenses/bsd-license.php
> +//
> +//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//
> +//
> +
> +#/**
> +#  Unmodified from:
> +#   ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
> +#
> +#**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Base.h>
> +#include <Library/PcdLib.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_IMPORT(CEntryPoint)
> +GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +GCC_ASM_IMPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(_ModuleEntryPoint)
> +
> +StartupAddr: .8byte CEntryPoint
> +
> +ASM_PFX(_ModuleEntryPoint):
> +  // Do early platform specific actions
> +  bl    ASM_PFX(ArmPlatformPeiBootAction)
> +
> +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
> +//       and configure the system accordingly. EL2 is default if possible.
> +// If we started in EL3 we need to switch and run at EL2.
> +// If we are running at EL2 stay in EL2
> +// If we are starting at EL1 stay in EL1.
> +
> +// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
> +// If started at EL1 or EL2 Sec jumps directly to PEI without making any
> +// changes.
> +
> +// Which EL are we running at? Every EL needs some level of setup...
> +// We should not run this code in EL3
> +  EL1_OR_EL2(x0)
> +1:bl    ASM_PFX(SetupExceptionLevel1)
> +  b     ASM_PFX(MainEntryPoint)
> +2:bl    ASM_PFX(SetupExceptionLevel2)
> +  b     ASM_PFX(MainEntryPoint)
> +
> +ASM_PFX(MainEntryPoint):
> +  // Identify CPU ID
> +  bl    ASM_PFX(ArmReadMpidr)
> +  // Keep a copy of the MpId register value
> +  mov   x5, x0
> +
> +  // Is it the Primary Core ?
> +  bl    ASM_PFX(ArmPlatformIsPrimaryCore)
> +
> +  // Get the top of the primary stacks (and the base of the secondary stacks)
> +  LoadConstantToReg (FixedPcdGet64(PcdCPUCoresStackBase), x1)
> +  LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)
> +  add   x1, x1, x2
> +
> +  // x0 is equal to 1 if I am the primary core
> +  cmp   x0, #1
> +  b.eq   _SetupPrimaryCoreStack
> +
> +_SetupSecondaryCoreStack:
> +  // x1 contains the base of the secondary stacks
> +
> +  // Get the Core Position
> +  mov   x6, x1      // Save base of the secondary stacks
> +  mov   x0, x5
> +  bl    ASM_PFX(ArmPlatformGetCorePosition)
> +  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
> +  add   x0, x0, #1
> +
> +  // StackOffset = CorePos * StackSize
> +  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)
> +  mul   x0, x0, x2
> +  // SP = StackBase + StackOffset
> +  add   sp, x6, x0
> +
> +_PrepareArguments:
> +  // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
> +  LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)
> +  add   x2, x2, #8
> +  ldr   x1, [x2]
> +
> +  // Move sec startup address into a data register
> +  // Ensure we're jumping to FV version of the code (not boot remapped alias)
> +  ldr   x3, StartupAddr
> +
> +  // Jump to PrePeiCore C code
> +  //    x0 = mp_id
> +  //    x1 = pei_core_address
> +  mov   x0, x5
> +  blr   x3
> +
> +_SetupPrimaryCoreStack:
> +  mov   sp, x1
> +  b     _PrepareArguments
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
> new file mode 100644
> index 0000000..8414d29
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
> @@ -0,0 +1,49 @@
> +#------------------------------------------------------------------------------
> +#
> +# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
> +# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution.  The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#------------------------------------------------------------------------------
> +#/**
> +#  Unmodified from:
> +#   ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
> +#
> +#**/
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(SecSwitchStack)
> +
> +
> +
> +#/**
> +#  This allows the caller to switch the stack and return
> +#
> +# @param      StackDelta     Signed amount by which to modify the stack pointer
> +#
> +# @return     Nothing. Goes to the Entry Point passing in the new parameters
> +#
> +#**/
> +#VOID
> +#EFIAPI
> +#SecSwitchStack (
> +#  VOID  *StackDelta
> +#  )#
> +#
> +ASM_PFX(SecSwitchStack):
> +    mov   x1, sp
> +    add   x1, x0, x1
> +    mov   sp, x1
> +    ret
> +
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
> new file mode 100644
> index 0000000..c708f84
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
> @@ -0,0 +1,168 @@
> +/** @file
> +*
> +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +*  Copyright (c) 2016, AMD Inc. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +/**
> +  Derived from:
> +   ArmPlatformPkg/PrePeiCore/MainMPCore.c
> +
> +  Adds MmioWrite64() for 64-bit mailbox pointers.
> +
> +**/
> +
> +#include <Library/ArmGicLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +#include "PrePeiCore.h"
> +
> +/*
> + * This is the main function for secondary cores. They loop around until a non Null value is written to
> + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
> + * Note:The secondary cores, while executing secondary_main, assumes that:
> + *      : SGI 0 is configured as Non-secure interrupt
> + *      : Priority Mask is configured to allow SGI 0
> + *      : Interrupt Distributor and CPU interfaces are enabled
> + *
> + */
> +VOID
> +EFIAPI
> +SecondaryMain (
> +  IN UINTN MpId
> +  )
> +{
> +  EFI_STATUS              Status;
> +  UINTN                   PpiListSize;
> +  UINTN                   PpiListCount;
> +  EFI_PEI_PPI_DESCRIPTOR  *PpiList;
> +  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
> +  UINTN                   Index;
> +  UINTN                   ArmCoreCount;
> +  ARM_CORE_INFO           *ArmCoreInfoTable;
> +  UINT32                  ClusterId;
> +  UINT32                  CoreId;
> +  VOID                    (*SecondaryStart)(VOID);
> +  UINTN                   SecondaryEntryAddr;
> +  UINTN                   AcknowledgeInterrupt;
> +  UINTN                   InterruptId;
> +
> +  ClusterId = GET_CLUSTER_ID(MpId);
> +  CoreId    = GET_CORE_ID(MpId);
> +
> +  // Get the gArmMpCoreInfoPpiGuid
> +  PpiListSize = 0;
> +  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
> +  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
> +  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
> +    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
> +      break;
> +    }
> +  }
> +
> +  // On MP Core Platform we must implement the ARM MP Core Info PPI
> +  ASSERT (Index != PpiListCount);
> +
> +  ArmMpCoreInfoPpi = PpiList->Ppi;
> +  ArmCoreCount = 0;
> +  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  // Find the core in the ArmCoreTable
> +  for (Index = 0; Index < ArmCoreCount; Index++) {
> +    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
> +      break;
> +    }
> +  }
> +
> +  // The ARM Core Info Table must define every core
> +  ASSERT (Index != ArmCoreCount);
> +
> +  // Clear Secondary cores MailBox
> +  if (sizeof(UINTN) == sizeof(UINT64))
> +    MmioWrite64 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
> +  else
> +    MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
> +
> +  do {
> +    ArmCallWFI ();
> +
> +    // Read the Mailbox
> +    if (sizeof(UINTN) == sizeof(UINT64))
> +      SecondaryEntryAddr = MmioRead64 (ArmCoreInfoTable[Index].MailboxGetAddress);
> +    else
> +      SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
> +
> +    // Acknowledge the interrupt and send End of Interrupt signal.
> +    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);
> +    // Check if it is a valid interrupt ID
> +    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
> +      // Got a valid SGI number hence signal End of Interrupt
> +      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
> +    }
> +  } while (SecondaryEntryAddr == 0);
> +
> +  // Jump to secondary core entry point.
> +  SecondaryStart = (VOID (*)())SecondaryEntryAddr;
> +  SecondaryStart();
> +
> +  // The secondaries shouldn't reach here
> +  ASSERT(FALSE);
> +}
> +
> +VOID
> +EFIAPI
> +PrimaryMain (
> +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
> +  )
> +{
> +  EFI_SEC_PEI_HAND_OFF        SecCoreData;
> +  UINTN                       PpiListSize;
> +  EFI_PEI_PPI_DESCRIPTOR      *PpiList;
> +  UINTN                       TemporaryRamBase;
> +  UINTN                       TemporaryRamSize;
> +
> +  CreatePpiList (&PpiListSize, &PpiList);
> +
> +  // Enable the GIC Distributor
> +  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
> +
> +  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
> +  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
> +    // Sending SGI to all the Secondary CPU interfaces
> +    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
> +  }
> +
> +  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
> +  // the base of the primary core stack
> +  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
> +  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
> +  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
> +
> +  //
> +  // Bind this information into the SEC hand-off state
> +  // Note: this must be in sync with the stuff in the asm file
> +  // Note also:  HOBs (pei temp ram) MUST be above stack
> +  //
> +  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
> +  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
> +  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
> +  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
> +  SecCoreData.TemporaryRamSize       = TemporaryRamSize;
> +  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
> +  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
> +  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
> +  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
> +
> +  // Jump to PEI core entry point
> +  PeiCoreEntryPoint (&SecCoreData, PpiList);
> +}
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> new file mode 100644
> index 0000000..7b45c00
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> @@ -0,0 +1,149 @@
> +/** @file
> +*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
> +*
> +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +*  Copyright (c) 2016, AMD Inc. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +/**
> +  Unmodified from:
> +   ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugAgentLib.h>
> +#include <Library/ArmLib.h>
> +
> +#include "PrePeiCore.h"
> +
> +CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI   mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
> +
> +CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
> +    &gEfiTemporaryRamSupportPpiGuid,
> +    (VOID *) &mTemporaryRamSupportPpi
> +  }
> +};
> +
> +VOID
> +CreatePpiList (
> +  OUT UINTN                   *PpiListSize,
> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
> +  )
> +{
> +  EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
> +  UINTN                   PlatformPpiListSize;
> +  UINTN                   ListBase;
> +  EFI_PEI_PPI_DESCRIPTOR *LastPpi;
> +
> +  // Get the Platform PPIs
> +  PlatformPpiListSize = 0;
> +  ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
> +
> +  // Copy the Common and Platform PPis in Temporrary Memory
> +  ListBase = PcdGet64 (PcdCPUCoresStackBase);
> +  CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));
> +  CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
> +
> +  // Set the Terminate flag on the last PPI entry
> +  LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;
> +  LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> +
> +  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;
> +  *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;
> +}
> +
> +VOID
> +CEntryPoint (
> +  IN  UINTN                     MpId,
> +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
> +  )
> +{
> +  // Data Cache enabled on Primary core when MMU is enabled.
> +  ArmDisableDataCache ();
> +  // Invalidate Data cache
> +  ArmInvalidateDataCache ();
> +  // Invalidate instruction cache
> +  ArmInvalidateInstructionCache ();
> +  // Enable Instruction Caches on all cores.
> +  ArmEnableInstructionCache ();
> +
> +  //
> +  // Note: Doesn't have to Enable CPU interface in non-secure world,
> +  // as Non-secure interface is already enabled in Secure world.
> +  //
> +
> +  // Write VBAR - The Exception Vector table must be aligned to its requirement
> +  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
> +  // 'Align=4K' is defined into your FDF for this module.
> +  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
> +  ArmWriteVBar ((UINTN)PeiVectorTable);
> +
> +  //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
> +
> +  // If not primary Jump to Secondary Main
> +  if (ArmPlatformIsPrimaryCore (MpId)) {
> +    // Initialize the Debug Agent for Source Level Debugging
> +    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
> +    SaveAndSetDebugTimerInterrupt (TRUE);
> +
> +    // Initialize the platform specific controllers
> +    ArmPlatformInitialize (MpId);
> +
> +    // Goto primary Main.
> +    PrimaryMain (PeiCoreEntryPoint);
> +  } else {
> +    SecondaryMain (MpId);
> +  }
> +
> +  // PEI Core should always load and never return
> +  ASSERT (FALSE);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PrePeiCoreTemporaryRamSupport (
> +  IN CONST EFI_PEI_SERVICES   **PeiServices,
> +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
> +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
> +  IN UINTN                    CopySize
> +  )
> +{
> +  VOID                             *OldHeap;
> +  VOID                             *NewHeap;
> +  VOID                             *OldStack;
> +  VOID                             *NewStack;
> +  UINTN                            HeapSize;
> +
> +  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
> +
> +  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
> +  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
> +
> +  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
> +  NewStack = (VOID*)(UINTN)PermanentMemoryBase;
> +
> +  //
> +  // Migrate the temporary memory stack to permanent memory stack.
> +  //
> +  CopyMem (NewStack, OldStack, CopySize - HeapSize);
> +
> +  //
> +  // Migrate the temporary memory heap to permanent memory heap.
> +  //
> +  CopyMem (NewHeap, OldHeap, HeapSize);
> +
> +  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> new file mode 100644
> index 0000000..334f086
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> @@ -0,0 +1,85 @@
> +/** @file
> +*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
> +*
> +*  Copyright (c) 2011, ARM Limited. All rights reserved.
> +*  Copyright (c) 2016, AMD Inc. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +/**
> +  Unmodified from:
> +   ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> +
> +**/
> +
> +#ifndef __PREPEICORE_H_
> +#define __PREPEICORE_H_
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include <PiPei.h>
> +#include <Ppi/TemporaryRamSupport.h>
> +
> +VOID
> +CreatePpiList (
> +  OUT UINTN                   *PpiListSize,
> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +PrePeiCoreTemporaryRamSupport (
> +  IN CONST EFI_PEI_SERVICES   **PeiServices,
> +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
> +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
> +  IN UINTN                    CopySize
> +  );
> +
> +VOID
> +SecSwitchStack (
> +  INTN    StackDelta
> +  );
> +
> +// Vector Table for Pei Phase
> +VOID  PeiVectorTable (VOID);
> +
> +VOID
> +EFIAPI
> +PrimaryMain (
> +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
> +  );
> +
> +/*
> + * This is the main function for secondary cores. They loop around until a non Null value is written to
> + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
> + * Note:The secondary cores, while executing secondary_main, assumes that:
> + *      : SGI 0 is configured as Non-secure interrupt
> + *      : Priority Mask is configured to allow SGI 0
> + *      : Interrupt Distributor and CPU interfaces are enabled
> + *
> + */
> +VOID
> +EFIAPI
> +SecondaryMain (
> +  IN UINTN MpId
> +  );
> +
> +VOID
> +PeiCommonExceptionEntry (
> +  IN UINT32 Entry,
> +  IN UINTN LR
> +  );
> +
> +#endif
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> new file mode 100644
> index 0000000..28b5b04
> --- /dev/null
> +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> @@ -0,0 +1,76 @@
> +#/** @file
> +#  Pre PeiCore - Hand-off to PEI Core in Normal World
> +#
> +#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +#  Copyright (c) 2016, AMD Inc. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +#/**
> +#  Derived from:
> +#   ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> +#
> +#  Removes [Sources.ARM] section
> +#
> +#**/
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010005
> +  BASE_NAME                      = ArmPlatformPrePeiCore
> +  FILE_GUID                      = 469fc080-aec1-11df-927c-0002a5d5c51b
> +  MODULE_TYPE                    = SEC
> +  VERSION_STRING                 = 1.0
> +
> +[Sources.common]
> +  MainMPCore.c
> +  PrePeiCore.c
> +
> +[Sources.AARCH64]
> +  AArch64/ArchPrePeiCore.c
> +  AArch64/PrePeiCoreEntryPoint.S
> +  AArch64/SwitchStack.S
> +  AArch64/Exception.S
> +  AArch64/Helper.S
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  ArmPkg/ArmPkg.dec
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  ArmPlatformLib
> +  BaseLib
> +  DebugLib
> +  DebugAgentLib
> +  IoLib
> +  ArmGicLib
> +  PrintLib
> +  SerialPortLib
> +
> +[Ppis]
> +  gEfiTemporaryRamSupportPpiGuid
> +  gArmMpCoreInfoPpiGuid
> +
> +[FeaturePcd]
> +  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdFvBaseAddress
> +  gArmTokenSpaceGuid.PcdFvSize
> +
> +  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
> +  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
> +  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
> +
> +  gArmTokenSpaceGuid.PcdGicDistributorBase
> +  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> +  gArmTokenSpaceGuid.PcdGicSgiIntId
> --
> 1.9.1
>
Duran, Leo May 1, 2016, 7:08 p.m. | #2
Considering that ARM_CORE_INFO define mailbox addresses as EFI_PHYSICAL_ADDRESS, it seems reasonable to allow 64-bit MMMIO access.
Leo.

typedef struct {
  UINT32                ClusterId;
  UINT32                CoreId;

  // MP Core Mailbox
  EFI_PHYSICAL_ADDRESS  MailboxSetAddress;
  EFI_PHYSICAL_ADDRESS  MailboxGetAddress;
  EFI_PHYSICAL_ADDRESS  MailboxClearAddress;
  UINT64                MailboxClearValue;
} ARM_CORE_INFO;

> -----Original Message-----

> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]

> Sent: Sunday, May 01, 2016 3:09 AM

> To: Duran, Leo <leo.duran@amd.com>

> Cc: Linaro UEFI Mailman List <linaro-uefi@lists.linaro.org>; Leif Lindholm

> <leif.lindholm@linaro.org>

> Subject: Re: [PATCH] Override PrePeiCoreMPCore to allow 64-bit mailbox

> pointers

> 

> On 30 April 2016 at 01:40, Leo Duran <leo.duran@amd.com> wrote:

> > This patch supersedes PATCH 4/4 of the previous series.

> > The path to the Override files is now correct.

> >

> 

> Actually, after thinking about this a bit more, I think it is not Overdrive that

> needs the override but VExpress. I will propose patches to make FVP and

> Juno PSCI only, allowing us to turn the current MPCore implementation into a

> 32-bit VExpress specific one. Next, I will propose a new implementation that

> more closely resembles what we need to do to implement the ACPI parking

> protocol (i.e., 1 reserved page per core, etc etc), which should support

> Overdrive in non-PSCI mode but also other implementations like Xgene

> which boots in EL2

> 

> 

> > Contributed-under: TianoCore Contribution Agreement 1.0

> > Signed-off-by: Leo Duran <leo.duran@amd.com>

> > ---

> >  .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc     |   2 +-

> >  .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf     |   2 +-

> >  .../PrePeiCore/AArch64/ArchPrePeiCore.c            |  58 +++++++

> >  .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S  | 126

> ++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S     |  54 +++++++

> >  .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S      | 112

> ++++++++++++++

> >  .../PrePeiCore/AArch64/SwitchStack.S               |  49 ++++++

> >  .../ArmPlatformPkg/PrePeiCore/MainMPCore.c         | 168

> +++++++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c         | 149

> ++++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h         |  85 +++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf |  76 ++++++++++

> >  11 files changed, 879 insertions(+), 2 deletions(-)  create mode

> > 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/ArchPrePeiCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/Exception.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/Helper.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/PrePeiCoreEntryPoint.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/SwitchStack.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/M

> > ainMPCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCore.h  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCoreMPCore.inf

> >

> > diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > index e83a8ef..6ee7181 100644

> > --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > @@ -561,7 +561,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2)  !if

> $(DO_PSCI)

> >    ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf

> >  !else

> > -  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +

> > +

> OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatf

> o

> > + rmPkg/PrePeiCore/PrePeiCoreMPCore.inf

> >  !endif

> >    MdeModulePkg/Core/Pei/PeiMain.inf

> >    MdeModulePkg/Universal/PCD/Pei/Pcd.inf { diff --git

> > a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > index cbfb6c3..0134af2 100644

> > --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > @@ -250,7 +250,7 @@ READ_LOCK_STATUS   = TRUE

> >  !if $(DO_PSCI)

> >    INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf

> >  !else

> > -  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +  INF

> > +

> OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatf

> o

> > + rmPkg/PrePeiCore/PrePeiCoreMPCore.inf

> >  !endif

> >    INF MdeModulePkg/Core/Pei/PeiMain.inf

> >    INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/ArchPrePeiCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/ArchPrePeiCore.c

> > new file mode 100644

> > index 0000000..9f86d3e

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/ArchPrePeiCore.c

> > @@ -0,0 +1,58 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions of

> > +the BSD License

> > +*  which accompanies this distribution.  The full text of the license

> > +may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c

> > +

> > +**/

> > +

> > +#include <Library/PrintLib.h>

> > +#include <Library/SerialPortLib.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +VOID

> > +PeiCommonExceptionEntry (

> > +  IN UINT32 Entry,

> > +  IN UINTN LR

> > +  )

> > +{

> > +  CHAR8           Buffer[100];

> > +  UINTN           CharCount;

> > +

> > +  switch (Entry) {

> > +  case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception

> at 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_IRQ:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at

> 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_FIQ:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at

> 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_SERROR:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception

> at 0x%X\n\r", LR);

> > +    break;

> > +  default:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at

> 0x%X\n\r", LR);

> > +    break;

> > +  }

> > +

> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);

> > +

> > +  while(1);

> > +}

> > +

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Exception.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Exception.S

> > new file mode 100644

> > index 0000000..38a4257

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/Exception.S

> > @@ -0,0 +1,126 @@

> > +#

> > +#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and

> > +made available under the terms and conditions of the BSD License #

> > +which accompanies this distribution.  The full text of the license

> > +may be found at #  http://opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/Exception.S

> > +#

> > +#**/

> > +

> > +#include <Chipset/AArch64.h>

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Base.h>

> > +#include <AutoGen.h>

> > +

> > +.text

> > +

> >

> +//========================================================

> ====

> > +//Default Exception Handlers

> >

> +//========================================================

> ====

> > +

> > +#define TO_HANDLER                                              \

> > +   EL1_OR_EL2(x1)                                               \

> > +1: mrs  x1, elr_el1    /* EL1 Exception Link Register */       ;\

> > +   b    3f                                                     ;\

> > +2: mrs  x1, elr_el2    /* EL2 Exception Link Register */       ;\

> > +3: bl   ASM_PFX(PeiCommonExceptionEntry)                       ;

> > +

> > +

> > +//

> > +// Default Exception handlers: There is no plan to return from any of

> these exceptions.

> > +// No context saving at all.

> > +//

> > +

> > +VECTOR_BASE(PeiVectorTable)

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)

> > +_DefaultSyncExceptHandler_t:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)

> > +_DefaultIrq_t:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)

> > +_DefaultFiq_t:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)

> > +_DefaultSError_t:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)

> > +_DefaultSyncExceptHandler_h:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)

> > +_DefaultIrq_h:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)

> > +_DefaultFiq_h:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)

> > +_DefaultSError_h:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)

> > +_DefaultSyncExceptHandler_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)

> > +_DefaultIrq_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)

> > +_DefaultFiq_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)

> > +_DefaultSError_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)

> > +_DefaultSyncExceptHandler_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)

> > +_DefaultIrq_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)

> > +_DefaultFiq_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)

> > +_DefaultSError_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_END(PeiVectorTable)

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Helper.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Helper.S

> > new file mode 100644

> > index 0000000..b9a0049

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/Helper.S

> > @@ -0,0 +1,54 @@

> >

> +#========================================================

> ============

> > +==================== #  Copyright (c) 2011-2013, ARM Limited. All

> > +rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and

> > +made available under the terms and conditions of the BSD License #

> > +which accompanies this distribution.  The full text of the license

> > +may be found at #  http:#opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> >

> +#========================================================

> ============

> > +===================

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/Helper.S

> > +#

> > +#**/

> > +

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Chipset/AArch64.h>

> > +

> > +#start of the code section

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_EXPORT(SetupExceptionLevel1)

> > +GCC_ASM_EXPORT(SetupExceptionLevel2)

> > +

> > +// Setup EL1 while in EL1

> > +ASM_PFX(SetupExceptionLevel1):

> > +   mov  x5, x30                   // Save LR

> > +

> > +   mov  x0, #CPACR_CP_FULL_ACCESS

> > +   bl   ASM_PFX(ArmWriteCpacr)    // Disable copro traps to EL1

> > +

> > +   ret  x5

> > +

> > +// Setup EL2 while in EL2

> > +ASM_PFX(SetupExceptionLevel2):

> > +   msr     sctlr_el2, xzr

> > +   mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register

> > +

> > +   // Send all interrupts to their respective Exception levels for EL2

> > +   orr     x0, x0, #(1 << 3)      // Enable EL2 FIQ

> > +   orr     x0, x0, #(1 << 4)      // Enable EL2 IRQ

> > +   orr     x0, x0, #(1 << 5)      // Enable EL2 SError and Abort

> > +   msr     hcr_el2, x0            // Write back our settings

> > +

> > +   msr     cptr_el2, xzr          // Disable copro traps to EL2

> > +

> > +   ret

> > +

> > +ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/PrePeiCoreEntryPoint.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/PrePeiCoreEntryPoint.S

> > new file mode 100644

> > index 0000000..2ddf4d4

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/PrePeiCoreEntryPoint.S

> > @@ -0,0 +1,112 @@

> > +//

> > +//  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +//  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +//

> > +//  This program and the accompanying materials //  are licensed and

> > +made available under the terms and conditions of the BSD License //

> > +which accompanies this distribution.  The full text of the license

> > +may be found at //  http://opensource.org/licenses/bsd-license.php

> > +//

> > +//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +//

> > +//

> > +

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S

> > +#

> > +#**/

> > +

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Base.h>

> > +#include <Library/PcdLib.h>

> > +#include <AutoGen.h>

> > +

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_IMPORT(CEntryPoint)

> > +GCC_ASM_IMPORT(ArmPlatformGetCorePosition)

> > +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)

> > +GCC_ASM_IMPORT(ArmReadMpidr)

> > +GCC_ASM_IMPORT(ArmPlatformPeiBootAction)

> > +GCC_ASM_EXPORT(_ModuleEntryPoint)

> > +

> > +StartupAddr: .8byte CEntryPoint

> > +

> > +ASM_PFX(_ModuleEntryPoint):

> > +  // Do early platform specific actions

> > +  bl    ASM_PFX(ArmPlatformPeiBootAction)

> > +

> > +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly

> detect

> > +//       and configure the system accordingly. EL2 is default if possible.

> > +// If we started in EL3 we need to switch and run at EL2.

> > +// If we are running at EL2 stay in EL2 // If we are starting at EL1

> > +stay in EL1.

> > +

> > +// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.

> > +// If started at EL1 or EL2 Sec jumps directly to PEI without making

> > +any // changes.

> > +

> > +// Which EL are we running at? Every EL needs some level of setup...

> > +// We should not run this code in EL3

> > +  EL1_OR_EL2(x0)

> > +1:bl    ASM_PFX(SetupExceptionLevel1)

> > +  b     ASM_PFX(MainEntryPoint)

> > +2:bl    ASM_PFX(SetupExceptionLevel2)

> > +  b     ASM_PFX(MainEntryPoint)

> > +

> > +ASM_PFX(MainEntryPoint):

> > +  // Identify CPU ID

> > +  bl    ASM_PFX(ArmReadMpidr)

> > +  // Keep a copy of the MpId register value

> > +  mov   x5, x0

> > +

> > +  // Is it the Primary Core ?

> > +  bl    ASM_PFX(ArmPlatformIsPrimaryCore)

> > +

> > +  // Get the top of the primary stacks (and the base of the secondary

> > + stacks)  LoadConstantToReg (FixedPcdGet64(PcdCPUCoresStackBase),

> x1)

> > + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)

> > +  add   x1, x1, x2

> > +

> > +  // x0 is equal to 1 if I am the primary core

> > +  cmp   x0, #1

> > +  b.eq   _SetupPrimaryCoreStack

> > +

> > +_SetupSecondaryCoreStack:

> > +  // x1 contains the base of the secondary stacks

> > +

> > +  // Get the Core Position

> > +  mov   x6, x1      // Save base of the secondary stacks

> > +  mov   x0, x5

> > +  bl    ASM_PFX(ArmPlatformGetCorePosition)

> > +  // The stack starts at the top of the stack region. Add '1' to the Core

> Position to get the top of the stack

> > +  add   x0, x0, #1

> > +

> > +  // StackOffset = CorePos * StackSize  LoadConstantToReg

> > + (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)

> > +  mul   x0, x0, x2

> > +  // SP = StackBase + StackOffset

> > +  add   sp, x6, x0

> > +

> > +_PrepareArguments:

> > +  // The PEI Core Entry Point has been computed by GenFV and stored

> > +in the second entry of the Reset Vector

> > +  LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)

> > +  add   x2, x2, #8

> > +  ldr   x1, [x2]

> > +

> > +  // Move sec startup address into a data register  // Ensure we're

> > + jumping to FV version of the code (not boot remapped alias)

> > +  ldr   x3, StartupAddr

> > +

> > +  // Jump to PrePeiCore C code

> > +  //    x0 = mp_id

> > +  //    x1 = pei_core_address

> > +  mov   x0, x5

> > +  blr   x3

> > +

> > +_SetupPrimaryCoreStack:

> > +  mov   sp, x1

> > +  b     _PrepareArguments

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/SwitchStack.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/SwitchStack.S

> > new file mode 100644

> > index 0000000..8414d29

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/SwitchStack.S

> > @@ -0,0 +1,49 @@

> > +#--------------------------------------------------------------------

> > +----------

> > +#

> > +# Copyright (c) 2006 - 2009, Intel Corporation. All rights

> > +reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All

> > +rights reserved.<BR> # Portions copyright (c) 2011 - 2013, ARM Ltd.

> > +All rights reserved.<BR> # Copyright (c) 2016, AMD Inc. All rights

> > +reserved.<BR> # # This program and the accompanying materials # are

> > +licensed and made available under the terms and conditions of the BSD

> > +License # which accompanies this distribution.  The full text of the

> > +license may be found at # http://opensource.org/licenses/bsd-

> license.php.

> > +#

> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#--------------------------------------------------------------------

> > +----------

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S

> > +#

> > +#**/

> > +

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_EXPORT(SecSwitchStack)

> > +

> > +

> > +

> > +#/**

> > +#  This allows the caller to switch the stack and return #

> > +# @param      StackDelta     Signed amount by which to modify the stack

> pointer

> > +#

> > +# @return     Nothing. Goes to the Entry Point passing in the new

> parameters

> > +#

> > +#**/

> > +#VOID

> > +#EFIAPI

> > +#SecSwitchStack (

> > +#  VOID  *StackDelta

> > +#  )#

> > +#

> > +ASM_PFX(SecSwitchStack):

> > +    mov   x1, sp

> > +    add   x1, x0, x1

> > +    mov   sp, x1

> > +    ret

> > +

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /MainMPCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /MainMPCore.c

> > new file mode 100644

> > index 0000000..c708f84

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/MainMPCore.c

> > @@ -0,0 +1,168 @@

> > +/** @file

> > +*

> > +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions of

> > +the BSD License

> > +*  which accompanies this distribution.  The full text of the license

> > +may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Derived from:

> > +   ArmPlatformPkg/PrePeiCore/MainMPCore.c

> > +

> > +  Adds MmioWrite64() for 64-bit mailbox pointers.

> > +

> > +**/

> > +

> > +#include <Library/ArmGicLib.h>

> > +

> > +#include <Ppi/ArmMpCoreInfo.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +/*

> > + * This is the main function for secondary cores. They loop around

> > +until a non Null value is written to

> > + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

> > + * Note:The secondary cores, while executing secondary_main, assumes

> that:

> > + *      : SGI 0 is configured as Non-secure interrupt

> > + *      : Priority Mask is configured to allow SGI 0

> > + *      : Interrupt Distributor and CPU interfaces are enabled

> > + *

> > + */

> > +VOID

> > +EFIAPI

> > +SecondaryMain (

> > +  IN UINTN MpId

> > +  )

> > +{

> > +  EFI_STATUS              Status;

> > +  UINTN                   PpiListSize;

> > +  UINTN                   PpiListCount;

> > +  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

> > +  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;

> > +  UINTN                   Index;

> > +  UINTN                   ArmCoreCount;

> > +  ARM_CORE_INFO           *ArmCoreInfoTable;

> > +  UINT32                  ClusterId;

> > +  UINT32                  CoreId;

> > +  VOID                    (*SecondaryStart)(VOID);

> > +  UINTN                   SecondaryEntryAddr;

> > +  UINTN                   AcknowledgeInterrupt;

> > +  UINTN                   InterruptId;

> > +

> > +  ClusterId = GET_CLUSTER_ID(MpId);

> > +  CoreId    = GET_CORE_ID(MpId);

> > +

> > +  // Get the gArmMpCoreInfoPpiGuid

> > +  PpiListSize = 0;

> > +  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);

> > + PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);  for

> > + (Index = 0; Index < PpiListCount; Index++, PpiList++) {

> > +    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {

> > +      break;

> > +    }

> > +  }

> > +

> > +  // On MP Core Platform we must implement the ARM MP Core Info PPI

> > + ASSERT (Index != PpiListCount);

> > +

> > +  ArmMpCoreInfoPpi = PpiList->Ppi;

> > +  ArmCoreCount = 0;

> > +  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount,

> > + &ArmCoreInfoTable);  ASSERT_EFI_ERROR (Status);

> > +

> > +  // Find the core in the ArmCoreTable  for (Index = 0; Index <

> > + ArmCoreCount; Index++) {

> > +    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) &&

> (ArmCoreInfoTable[Index].CoreId == CoreId)) {

> > +      break;

> > +    }

> > +  }

> > +

> > +  // The ARM Core Info Table must define every core  ASSERT (Index !=

> > + ArmCoreCount);

> > +

> > +  // Clear Secondary cores MailBox

> > +  if (sizeof(UINTN) == sizeof(UINT64))

> > +    MmioWrite64 (ArmCoreInfoTable[Index].MailboxClearAddress,

> > + ArmCoreInfoTable[Index].MailboxClearValue);

> > +  else

> > +    MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,

> > + ArmCoreInfoTable[Index].MailboxClearValue);

> > +

> > +  do {

> > +    ArmCallWFI ();

> > +

> > +    // Read the Mailbox

> > +    if (sizeof(UINTN) == sizeof(UINT64))

> > +      SecondaryEntryAddr = MmioRead64

> (ArmCoreInfoTable[Index].MailboxGetAddress);

> > +    else

> > +      SecondaryEntryAddr = MmioRead32

> > + (ArmCoreInfoTable[Index].MailboxGetAddress);

> > +

> > +    // Acknowledge the interrupt and send End of Interrupt signal.

> > +    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32

> (PcdGicInterruptInterfaceBase), &InterruptId);

> > +    // Check if it is a valid interrupt ID

> > +    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32

> (PcdGicDistributorBase))) {

> > +      // Got a valid SGI number hence signal End of Interrupt

> > +      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase),

> AcknowledgeInterrupt);

> > +    }

> > +  } while (SecondaryEntryAddr == 0);

> > +

> > +  // Jump to secondary core entry point.

> > +  SecondaryStart = (VOID (*)())SecondaryEntryAddr;  SecondaryStart();

> > +

> > +  // The secondaries shouldn't reach here

> > +  ASSERT(FALSE);

> > +}

> > +

> > +VOID

> > +EFIAPI

> > +PrimaryMain (

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  )

> > +{

> > +  EFI_SEC_PEI_HAND_OFF        SecCoreData;

> > +  UINTN                       PpiListSize;

> > +  EFI_PEI_PPI_DESCRIPTOR      *PpiList;

> > +  UINTN                       TemporaryRamBase;

> > +  UINTN                       TemporaryRamSize;

> > +

> > +  CreatePpiList (&PpiListSize, &PpiList);

> > +

> > +  // Enable the GIC Distributor

> > +  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));

> > +

> > +  // If ArmVe has not been built as Standalone then we need to wake

> > + up the secondary cores  if (FeaturePcdGet

> (PcdSendSgiToBringUpSecondaryCores)) {

> > +    // Sending SGI to all the Secondary CPU interfaces

> > +    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase),

> > + ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32

> > + (PcdGicSgiIntId));  }

> > +

> > +  // Adjust the Temporary Ram as the new Ppi List (Common + Platform

> > + Ppi Lists) is created at  // the base of the primary core stack

> > + PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);

> > + TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) +

> > + PpiListSize;  TemporaryRamSize = (UINTN)PcdGet32

> > + (PcdCPUCorePrimaryStackSize) - PpiListSize;

> > +

> > +  //

> > +  // Bind this information into the SEC hand-off state  // Note: this

> > + must be in sync with the stuff in the asm file  // Note also:  HOBs

> > + (pei temp ram) MUST be above stack  //

> > +  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

> > +  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64

> > + (PcdFvBaseAddress);  SecCoreData.BootFirmwareVolumeSize =

> PcdGet32 (PcdFvSize);

> > +  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; //

> We run on the primary core (and so we use the first stack)

> > +  SecCoreData.TemporaryRamSize       = TemporaryRamSize;

> > +  SecCoreData.PeiTemporaryRamBase    =

> SecCoreData.TemporaryRamBase;

> > +  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE

> (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);

> > +  SecCoreData.StackBase              = (VOID

> *)((UINTN)SecCoreData.TemporaryRamBase +

> SecCoreData.PeiTemporaryRamSize);

> > +  SecCoreData.StackSize              = (TemporaryRamBase +

> TemporaryRamSize) - (UINTN)SecCoreData.StackBase;

> > +

> > +  // Jump to PEI core entry point

> > +  PeiCoreEntryPoint (&SecCoreData, PpiList); }

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.c

> > new file mode 100644

> > index 0000000..7b45c00

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCore.c

> > @@ -0,0 +1,149 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions of

> > +the BSD License

> > +*  which accompanies this distribution.  The full text of the license

> > +may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/PrePeiCore.c

> > +

> > +**/

> > +

> > +#include <Library/BaseLib.h>

> > +#include <Library/DebugAgentLib.h>

> > +#include <Library/ArmLib.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI

> mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };

> > +

> > +CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {

> > +  {

> > +    EFI_PEI_PPI_DESCRIPTOR_PPI,

> > +    &gEfiTemporaryRamSupportPpiGuid,

> > +    (VOID *) &mTemporaryRamSupportPpi

> > +  }

> > +};

> > +

> > +VOID

> > +CreatePpiList (

> > +  OUT UINTN                   *PpiListSize,

> > +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList

> > +  )

> > +{

> > +  EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;

> > +  UINTN                   PlatformPpiListSize;

> > +  UINTN                   ListBase;

> > +  EFI_PEI_PPI_DESCRIPTOR *LastPpi;

> > +

> > +  // Get the Platform PPIs

> > +  PlatformPpiListSize = 0;

> > +  ArmPlatformGetPlatformPpiList (&PlatformPpiListSize,

> > + &PlatformPpiList);

> > +

> > +  // Copy the Common and Platform PPis in Temporrary Memory  ListBase

> > + = PcdGet64 (PcdCPUCoresStackBase);  CopyMem ((VOID*)ListBase,

> > + gCommonPpiTable, sizeof(gCommonPpiTable));  CopyMem

> > + ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList,

> > + PlatformPpiListSize);

> > +

> > +  // Set the Terminate flag on the last PPI entry  LastPpi =

> > + (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) +

> > + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;

> > + LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

> > +

> > +  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;

> > +  *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize; }

> > +

> > +VOID

> > +CEntryPoint (

> > +  IN  UINTN                     MpId,

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  )

> > +{

> > +  // Data Cache enabled on Primary core when MMU is enabled.

> > +  ArmDisableDataCache ();

> > +  // Invalidate Data cache

> > +  ArmInvalidateDataCache ();

> > +  // Invalidate instruction cache

> > +  ArmInvalidateInstructionCache ();

> > +  // Enable Instruction Caches on all cores.

> > +  ArmEnableInstructionCache ();

> > +

> > +  //

> > +  // Note: Doesn't have to Enable CPU interface in non-secure world,

> > + // as Non-secure interface is already enabled in Secure world.

> > +  //

> > +

> > +  // Write VBAR - The Exception Vector table must be aligned to its

> > + requirement  // Note: The AArch64 Vector table must be 2k-byte

> > + aligned - if this assertion fails ensure  // 'Align=4K' is defined into your FDF

> for this module.

> > +  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT)

> == 0);

> > + ArmWriteVBar ((UINTN)PeiVectorTable);

> > +

> > +  //Note: The MMU will be enabled by MemoryPeim. Only the primary

> core will have the MMU on.

> > +

> > +  // If not primary Jump to Secondary Main  if

> > + (ArmPlatformIsPrimaryCore (MpId)) {

> > +    // Initialize the Debug Agent for Source Level Debugging

> > +    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL,

> NULL);

> > +    SaveAndSetDebugTimerInterrupt (TRUE);

> > +

> > +    // Initialize the platform specific controllers

> > +    ArmPlatformInitialize (MpId);

> > +

> > +    // Goto primary Main.

> > +    PrimaryMain (PeiCoreEntryPoint);

> > +  } else {

> > +    SecondaryMain (MpId);

> > +  }

> > +

> > +  // PEI Core should always load and never return

> > +  ASSERT (FALSE);

> > +}

> > +

> > +EFI_STATUS

> > +EFIAPI

> > +PrePeiCoreTemporaryRamSupport (

> > +  IN CONST EFI_PEI_SERVICES   **PeiServices,

> > +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

> > +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

> > +  IN UINTN                    CopySize

> > +  )

> > +{

> > +  VOID                             *OldHeap;

> > +  VOID                             *NewHeap;

> > +  VOID                             *OldStack;

> > +  VOID                             *NewStack;

> > +  UINTN                            HeapSize;

> > +

> > +  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);

> > +

> > +  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;

> > +  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize -

> > + HeapSize));

> > +

> > +  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);

> > + NewStack = (VOID*)(UINTN)PermanentMemoryBase;

> > +

> > +  //

> > +  // Migrate the temporary memory stack to permanent memory stack.

> > +  //

> > +  CopyMem (NewStack, OldStack, CopySize - HeapSize);

> > +

> > +  //

> > +  // Migrate the temporary memory heap to permanent memory heap.

> > +  //

> > +  CopyMem (NewHeap, OldHeap, HeapSize);

> > +

> > +  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);

> > +

> > +  return EFI_SUCCESS;

> > +}

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.h

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.h

> > new file mode 100644

> > index 0000000..334f086

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCore.h

> > @@ -0,0 +1,85 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2011, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions of

> > +the BSD License

> > +*  which accompanies this distribution.  The full text of the license

> > +may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/PrePeiCore.h

> > +

> > +**/

> > +

> > +#ifndef __PREPEICORE_H_

> > +#define __PREPEICORE_H_

> > +

> > +#include <Library/ArmLib.h>

> > +#include <Library/ArmPlatformLib.h>

> > +#include <Library/BaseMemoryLib.h>

> > +#include <Library/DebugLib.h>

> > +#include <Library/IoLib.h>

> > +#include <Library/PcdLib.h>

> > +

> > +#include <PiPei.h>

> > +#include <Ppi/TemporaryRamSupport.h>

> > +

> > +VOID

> > +CreatePpiList (

> > +  OUT UINTN                   *PpiListSize,

> > +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList

> > +  );

> > +

> > +EFI_STATUS

> > +EFIAPI

> > +PrePeiCoreTemporaryRamSupport (

> > +  IN CONST EFI_PEI_SERVICES   **PeiServices,

> > +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

> > +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

> > +  IN UINTN                    CopySize

> > +  );

> > +

> > +VOID

> > +SecSwitchStack (

> > +  INTN    StackDelta

> > +  );

> > +

> > +// Vector Table for Pei Phase

> > +VOID  PeiVectorTable (VOID);

> > +

> > +VOID

> > +EFIAPI

> > +PrimaryMain (

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  );

> > +

> > +/*

> > + * This is the main function for secondary cores. They loop around

> > +until a non Null value is written to

> > + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

> > + * Note:The secondary cores, while executing secondary_main, assumes

> that:

> > + *      : SGI 0 is configured as Non-secure interrupt

> > + *      : Priority Mask is configured to allow SGI 0

> > + *      : Interrupt Distributor and CPU interfaces are enabled

> > + *

> > + */

> > +VOID

> > +EFIAPI

> > +SecondaryMain (

> > +  IN UINTN MpId

> > +  );

> > +

> > +VOID

> > +PeiCommonExceptionEntry (

> > +  IN UINT32 Entry,

> > +  IN UINTN LR

> > +  );

> > +

> > +#endif

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCoreMPCore.inf

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCoreMPCore.inf

> > new file mode 100644

> > index 0000000..28b5b04

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCoreMPCore.inf

> > @@ -0,0 +1,76 @@

> > +#/** @file

> > +#  Pre PeiCore - Hand-off to PEI Core in Normal World # #  Copyright

> > +(c) 2011-2014, ARM Limited. All rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and

> > +made available under the terms and conditions of the BSD License #

> > +which accompanies this distribution.  The full text of the license

> > +may be found at #  http://opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#**/

> > +#/**

> > +#  Derived from:

> > +#   ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +#

> > +#  Removes [Sources.ARM] section

> > +#

> > +#**/

> > +

> > +[Defines]

> > +  INF_VERSION                    = 0x00010005

> > +  BASE_NAME                      = ArmPlatformPrePeiCore

> > +  FILE_GUID                      = 469fc080-aec1-11df-927c-0002a5d5c51b

> > +  MODULE_TYPE                    = SEC

> > +  VERSION_STRING                 = 1.0

> > +

> > +[Sources.common]

> > +  MainMPCore.c

> > +  PrePeiCore.c

> > +

> > +[Sources.AARCH64]

> > +  AArch64/ArchPrePeiCore.c

> > +  AArch64/PrePeiCoreEntryPoint.S

> > +  AArch64/SwitchStack.S

> > +  AArch64/Exception.S

> > +  AArch64/Helper.S

> > +

> > +[Packages]

> > +  MdePkg/MdePkg.dec

> > +  MdeModulePkg/MdeModulePkg.dec

> > +  ArmPkg/ArmPkg.dec

> > +  ArmPlatformPkg/ArmPlatformPkg.dec

> > +

> > +[LibraryClasses]

> > +  ArmLib

> > +  ArmPlatformLib

> > +  BaseLib

> > +  DebugLib

> > +  DebugAgentLib

> > +  IoLib

> > +  ArmGicLib

> > +  PrintLib

> > +  SerialPortLib

> > +

> > +[Ppis]

> > +  gEfiTemporaryRamSupportPpiGuid

> > +  gArmMpCoreInfoPpiGuid

> > +

> > +[FeaturePcd]

> > +  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores

> > +

> > +[FixedPcd]

> > +  gArmTokenSpaceGuid.PcdFvBaseAddress

> > +  gArmTokenSpaceGuid.PcdFvSize

> > +

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize

> > +

> > +  gArmTokenSpaceGuid.PcdGicDistributorBase

> > +  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

> > +  gArmTokenSpaceGuid.PcdGicSgiIntId

> > --

> > 1.9.1

> >
Duran, Leo May 1, 2016, 10:27 p.m. | #3
Actually, I probably should have said:
Considering that ARM_CORE_INFO defines MailboxClearValue as UINT64, it seems reasonable to allow 64-bit MMMIO access.

Leo.
-----Original Message-----
From: Duran, Leo 

Sent: Sunday, May 01, 2016 2:08 PM
To: 'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Cc: Linaro UEFI Mailman List <linaro-uefi@lists.linaro.org>; Leif Lindholm <leif.lindholm@linaro.org>
Subject: RE: [PATCH] Override PrePeiCoreMPCore to allow 64-bit mailbox pointers

Considering that ARM_CORE_INFO defines mailbox addresses as EFI_PHYSICAL_ADDRESS, it seems reasonable to allow 64-bit MMMIO access.
Leo.

typedef struct {
  UINT32                ClusterId;
  UINT32                CoreId;

  // MP Core Mailbox
  EFI_PHYSICAL_ADDRESS  MailboxSetAddress;
  EFI_PHYSICAL_ADDRESS  MailboxGetAddress;
  EFI_PHYSICAL_ADDRESS  MailboxClearAddress;
  UINT64                MailboxClearValue;
} ARM_CORE_INFO;

> -----Original Message-----

> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]

> Sent: Sunday, May 01, 2016 3:09 AM

> To: Duran, Leo <leo.duran@amd.com>

> Cc: Linaro UEFI Mailman List <linaro-uefi@lists.linaro.org>; Leif 

> Lindholm <leif.lindholm@linaro.org>

> Subject: Re: [PATCH] Override PrePeiCoreMPCore to allow 64-bit mailbox 

> pointers

> 

> On 30 April 2016 at 01:40, Leo Duran <leo.duran@amd.com> wrote:

> > This patch supersedes PATCH 4/4 of the previous series.

> > The path to the Override files is now correct.

> >

> 

> Actually, after thinking about this a bit more, I think it is not 

> Overdrive that needs the override but VExpress. I will propose patches 

> to make FVP and Juno PSCI only, allowing us to turn the current MPCore 

> implementation into a 32-bit VExpress specific one. Next, I will 

> propose a new implementation that more closely resembles what we need 

> to do to implement the ACPI parking protocol (i.e., 1 reserved page 

> per core, etc etc), which should support Overdrive in non-PSCI mode 

> but also other implementations like Xgene which boots in EL2

> 

> 

> > Contributed-under: TianoCore Contribution Agreement 1.0

> > Signed-off-by: Leo Duran <leo.duran@amd.com>

> > ---

> >  .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc     |   2 +-

> >  .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf     |   2 +-

> >  .../PrePeiCore/AArch64/ArchPrePeiCore.c            |  58 +++++++

> >  .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S  | 126

> ++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S     |  54 +++++++

> >  .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S      | 112

> ++++++++++++++

> >  .../PrePeiCore/AArch64/SwitchStack.S               |  49 ++++++

> >  .../ArmPlatformPkg/PrePeiCore/MainMPCore.c         | 168

> +++++++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c         | 149

> ++++++++++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h         |  85 +++++++++++

> >  .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf |  76 ++++++++++

> >  11 files changed, 879 insertions(+), 2 deletions(-)  create mode

> > 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/ArchPrePeiCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/Exception.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/Helper.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/PrePeiCoreEntryPoint.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/A

> > Arch64/SwitchStack.S  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/M

> > ainMPCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCore.c  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCore.h  create mode 100644

> >

> Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCor

> e/P

> > rePeiCoreMPCore.inf

> >

> > diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > index e83a8ef..6ee7181 100644

> > --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc

> > @@ -561,7 +561,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2)  !if

> $(DO_PSCI)

> >    ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf

> >  !else

> > -  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +

> > +

> OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatf

> o

> > + rmPkg/PrePeiCore/PrePeiCoreMPCore.inf

> >  !endif

> >    MdeModulePkg/Core/Pei/PeiMain.inf

> >    MdeModulePkg/Universal/PCD/Pei/Pcd.inf { diff --git 

> > a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > index cbfb6c3..0134af2 100644

> > --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf

> > @@ -250,7 +250,7 @@ READ_LOCK_STATUS   = TRUE

> >  !if $(DO_PSCI)

> >    INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf

> >  !else

> > -  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +  INF

> > +

> OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatf

> o

> > + rmPkg/PrePeiCore/PrePeiCoreMPCore.inf

> >  !endif

> >    INF MdeModulePkg/Core/Pei/PeiMain.inf

> >    INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/ArchPrePeiCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/ArchPrePeiCore.c

> > new file mode 100644

> > index 0000000..9f86d3e

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/ArchPrePeiCore.c

> > @@ -0,0 +1,58 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World 

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions 

> > +of the BSD License

> > +*  which accompanies this distribution.  The full text of the 

> > +license may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c

> > +

> > +**/

> > +

> > +#include <Library/PrintLib.h>

> > +#include <Library/SerialPortLib.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +VOID

> > +PeiCommonExceptionEntry (

> > +  IN UINT32 Entry,

> > +  IN UINTN LR

> > +  )

> > +{

> > +  CHAR8           Buffer[100];

> > +  UINTN           CharCount;

> > +

> > +  switch (Entry) {

> > +  case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous 

> > + Exception

> at 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_IRQ:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception 

> > + at

> 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_FIQ:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception 

> > + at

> 0x%X\n\r", LR);

> > +    break;

> > +  case EXCEPT_AARCH64_SERROR:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort 

> > + Exception

> at 0x%X\n\r", LR);

> > +    break;

> > +  default:

> > +    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown 

> > + Exception at

> 0x%X\n\r", LR);

> > +    break;

> > +  }

> > +

> > +  SerialPortWrite ((UINT8 *) Buffer, CharCount);

> > +

> > +  while(1);

> > +}

> > +

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Exception.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Exception.S

> > new file mode 100644

> > index 0000000..38a4257

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/Exception.S

> > @@ -0,0 +1,126 @@

> > +#

> > +#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and 

> > +made available under the terms and conditions of the BSD License # 

> > +which accompanies this distribution.  The full text of the license 

> > +may be found at #  http://opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/Exception.S

> > +#

> > +#**/

> > +

> > +#include <Chipset/AArch64.h>

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Base.h>

> > +#include <AutoGen.h>

> > +

> > +.text

> > +

> >

> +//========================================================

> ====

> > +//Default Exception Handlers

> >

> +//========================================================

> ====

> > +

> > +#define TO_HANDLER                                              \

> > +   EL1_OR_EL2(x1)                                               \

> > +1: mrs  x1, elr_el1    /* EL1 Exception Link Register */       ;\

> > +   b    3f                                                     ;\

> > +2: mrs  x1, elr_el2    /* EL2 Exception Link Register */       ;\

> > +3: bl   ASM_PFX(PeiCommonExceptionEntry)                       ;

> > +

> > +

> > +//

> > +// Default Exception handlers: There is no plan to return from any 

> > +of

> these exceptions.

> > +// No context saving at all.

> > +//

> > +

> > +VECTOR_BASE(PeiVectorTable)

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)

> > +_DefaultSyncExceptHandler_t:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)

> > +_DefaultIrq_t:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)

> > +_DefaultFiq_t:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)

> > +_DefaultSError_t:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)

> > +_DefaultSyncExceptHandler_h:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)

> > +_DefaultIrq_h:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)

> > +_DefaultFiq_h:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)

> > +_DefaultSError_h:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)

> > +_DefaultSyncExceptHandler_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)

> > +_DefaultIrq_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)

> > +_DefaultFiq_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)

> > +_DefaultSError_LowerA64:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)

> > +_DefaultSyncExceptHandler_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)

> > +_DefaultIrq_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_IRQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)

> > +_DefaultFiq_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_FIQ

> > +  TO_HANDLER

> > +

> > +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)

> > +_DefaultSError_LowerA32:

> > +  mov  x0, #EXCEPT_AARCH64_SERROR

> > +  TO_HANDLER

> > +

> > +VECTOR_END(PeiVectorTable)

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Helper.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/Helper.S

> > new file mode 100644

> > index 0000000..b9a0049

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/Helper.S

> > @@ -0,0 +1,54 @@

> >

> +#========================================================

> ============

> > +==================== #  Copyright (c) 2011-2013, ARM Limited. All 

> > +rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and 

> > +made available under the terms and conditions of the BSD License # 

> > +which accompanies this distribution.  The full text of the license 

> > +may be found at #  http:#opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> >

> +#========================================================

> ============

> > +===================

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/Helper.S

> > +#

> > +#**/

> > +

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Chipset/AArch64.h>

> > +

> > +#start of the code section

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_EXPORT(SetupExceptionLevel1)

> > +GCC_ASM_EXPORT(SetupExceptionLevel2)

> > +

> > +// Setup EL1 while in EL1

> > +ASM_PFX(SetupExceptionLevel1):

> > +   mov  x5, x30                   // Save LR

> > +

> > +   mov  x0, #CPACR_CP_FULL_ACCESS

> > +   bl   ASM_PFX(ArmWriteCpacr)    // Disable copro traps to EL1

> > +

> > +   ret  x5

> > +

> > +// Setup EL2 while in EL2

> > +ASM_PFX(SetupExceptionLevel2):

> > +   msr     sctlr_el2, xzr

> > +   mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register

> > +

> > +   // Send all interrupts to their respective Exception levels for EL2

> > +   orr     x0, x0, #(1 << 3)      // Enable EL2 FIQ

> > +   orr     x0, x0, #(1 << 4)      // Enable EL2 IRQ

> > +   orr     x0, x0, #(1 << 5)      // Enable EL2 SError and Abort

> > +   msr     hcr_el2, x0            // Write back our settings

> > +

> > +   msr     cptr_el2, xzr          // Disable copro traps to EL2

> > +

> > +   ret

> > +

> > +ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/PrePeiCoreEntryPoint.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/PrePeiCoreEntryPoint.S

> > new file mode 100644

> > index 0000000..2ddf4d4

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/PrePeiCoreEntryPoint.S

> > @@ -0,0 +1,112 @@

> > +//

> > +//  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +//  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +//

> > +//  This program and the accompanying materials //  are licensed 

> > +and made available under the terms and conditions of the BSD 

> > +License // which accompanies this distribution.  The full text of 

> > +the license may be found at //  

> > +http://opensource.org/licenses/bsd-license.php

> > +//

> > +//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +//

> > +//

> > +

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S

> > +#

> > +#**/

> > +

> > +#include <AsmMacroIoLibV8.h>

> > +#include <Base.h>

> > +#include <Library/PcdLib.h>

> > +#include <AutoGen.h>

> > +

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_IMPORT(CEntryPoint)

> > +GCC_ASM_IMPORT(ArmPlatformGetCorePosition)

> > +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)

> > +GCC_ASM_IMPORT(ArmReadMpidr)

> > +GCC_ASM_IMPORT(ArmPlatformPeiBootAction)

> > +GCC_ASM_EXPORT(_ModuleEntryPoint)

> > +

> > +StartupAddr: .8byte CEntryPoint

> > +

> > +ASM_PFX(_ModuleEntryPoint):

> > +  // Do early platform specific actions

> > +  bl    ASM_PFX(ArmPlatformPeiBootAction)

> > +

> > +// NOTE: We could be booting from EL3, EL2 or EL1. Need to 

> > +correctly

> detect

> > +//       and configure the system accordingly. EL2 is default if possible.

> > +// If we started in EL3 we need to switch and run at EL2.

> > +// If we are running at EL2 stay in EL2 // If we are starting at 

> > +EL1 stay in EL1.

> > +

> > +// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.

> > +// If started at EL1 or EL2 Sec jumps directly to PEI without 

> > +making any // changes.

> > +

> > +// Which EL are we running at? Every EL needs some level of setup...

> > +// We should not run this code in EL3

> > +  EL1_OR_EL2(x0)

> > +1:bl    ASM_PFX(SetupExceptionLevel1)

> > +  b     ASM_PFX(MainEntryPoint)

> > +2:bl    ASM_PFX(SetupExceptionLevel2)

> > +  b     ASM_PFX(MainEntryPoint)

> > +

> > +ASM_PFX(MainEntryPoint):

> > +  // Identify CPU ID

> > +  bl    ASM_PFX(ArmReadMpidr)

> > +  // Keep a copy of the MpId register value

> > +  mov   x5, x0

> > +

> > +  // Is it the Primary Core ?

> > +  bl    ASM_PFX(ArmPlatformIsPrimaryCore)

> > +

> > +  // Get the top of the primary stacks (and the base of the 

> > + secondary

> > + stacks)  LoadConstantToReg (FixedPcdGet64(PcdCPUCoresStackBase),

> x1)

> > + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)

> > +  add   x1, x1, x2

> > +

> > +  // x0 is equal to 1 if I am the primary core

> > +  cmp   x0, #1

> > +  b.eq   _SetupPrimaryCoreStack

> > +

> > +_SetupSecondaryCoreStack:

> > +  // x1 contains the base of the secondary stacks

> > +

> > +  // Get the Core Position

> > +  mov   x6, x1      // Save base of the secondary stacks

> > +  mov   x0, x5

> > +  bl    ASM_PFX(ArmPlatformGetCorePosition)

> > +  // The stack starts at the top of the stack region. Add '1' to 

> > + the Core

> Position to get the top of the stack

> > +  add   x0, x0, #1

> > +

> > +  // StackOffset = CorePos * StackSize  LoadConstantToReg 

> > + (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)

> > +  mul   x0, x0, x2

> > +  // SP = StackBase + StackOffset

> > +  add   sp, x6, x0

> > +

> > +_PrepareArguments:

> > +  // The PEI Core Entry Point has been computed by GenFV and stored 

> > +in the second entry of the Reset Vector

> > +  LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)

> > +  add   x2, x2, #8

> > +  ldr   x1, [x2]

> > +

> > +  // Move sec startup address into a data register  // Ensure we're 

> > + jumping to FV version of the code (not boot remapped alias)

> > +  ldr   x3, StartupAddr

> > +

> > +  // Jump to PrePeiCore C code

> > +  //    x0 = mp_id

> > +  //    x1 = pei_core_address

> > +  mov   x0, x5

> > +  blr   x3

> > +

> > +_SetupPrimaryCoreStack:

> > +  mov   sp, x1

> > +  b     _PrepareArguments

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/SwitchStack.S

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /AArch64/SwitchStack.S

> > new file mode 100644

> > index 0000000..8414d29

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/AArch64/SwitchStack.S

> > @@ -0,0 +1,49 @@

> > +#------------------------------------------------------------------

> > +--

> > +----------

> > +#

> > +# Copyright (c) 2006 - 2009, Intel Corporation. All rights 

> > +reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All 

> > +rights reserved.<BR> # Portions copyright (c) 2011 - 2013, ARM Ltd.

> > +All rights reserved.<BR> # Copyright (c) 2016, AMD Inc. All rights 

> > +reserved.<BR> # # This program and the accompanying materials # are 

> > +licensed and made available under the terms and conditions of the 

> > +BSD License # which accompanies this distribution.  The full text 

> > +of the license may be found at # 

> > +http://opensource.org/licenses/bsd-

> license.php.

> > +#

> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#------------------------------------------------------------------

> > +--

> > +----------

> > +#/**

> > +#  Unmodified from:

> > +#   ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S

> > +#

> > +#**/

> > +

> > +.text

> > +.align 3

> > +

> > +GCC_ASM_EXPORT(SecSwitchStack)

> > +

> > +

> > +

> > +#/**

> > +#  This allows the caller to switch the stack and return #

> > +# @param      StackDelta     Signed amount by which to modify the stack

> pointer

> > +#

> > +# @return     Nothing. Goes to the Entry Point passing in the new

> parameters

> > +#

> > +#**/

> > +#VOID

> > +#EFIAPI

> > +#SecSwitchStack (

> > +#  VOID  *StackDelta

> > +#  )#

> > +#

> > +ASM_PFX(SecSwitchStack):

> > +    mov   x1, sp

> > +    add   x1, x0, x1

> > +    mov   sp, x1

> > +    ret

> > +

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /MainMPCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /MainMPCore.c

> > new file mode 100644

> > index 0000000..c708f84

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/MainMPCore.c

> > @@ -0,0 +1,168 @@

> > +/** @file

> > +*

> > +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions 

> > +of the BSD License

> > +*  which accompanies this distribution.  The full text of the 

> > +license may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Derived from:

> > +   ArmPlatformPkg/PrePeiCore/MainMPCore.c

> > +

> > +  Adds MmioWrite64() for 64-bit mailbox pointers.

> > +

> > +**/

> > +

> > +#include <Library/ArmGicLib.h>

> > +

> > +#include <Ppi/ArmMpCoreInfo.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +/*

> > + * This is the main function for secondary cores. They loop around 

> > +until a non Null value is written to

> > + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

> > + * Note:The secondary cores, while executing secondary_main, 

> > +assumes

> that:

> > + *      : SGI 0 is configured as Non-secure interrupt

> > + *      : Priority Mask is configured to allow SGI 0

> > + *      : Interrupt Distributor and CPU interfaces are enabled

> > + *

> > + */

> > +VOID

> > +EFIAPI

> > +SecondaryMain (

> > +  IN UINTN MpId

> > +  )

> > +{

> > +  EFI_STATUS              Status;

> > +  UINTN                   PpiListSize;

> > +  UINTN                   PpiListCount;

> > +  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

> > +  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;

> > +  UINTN                   Index;

> > +  UINTN                   ArmCoreCount;

> > +  ARM_CORE_INFO           *ArmCoreInfoTable;

> > +  UINT32                  ClusterId;

> > +  UINT32                  CoreId;

> > +  VOID                    (*SecondaryStart)(VOID);

> > +  UINTN                   SecondaryEntryAddr;

> > +  UINTN                   AcknowledgeInterrupt;

> > +  UINTN                   InterruptId;

> > +

> > +  ClusterId = GET_CLUSTER_ID(MpId);

> > +  CoreId    = GET_CORE_ID(MpId);

> > +

> > +  // Get the gArmMpCoreInfoPpiGuid

> > +  PpiListSize = 0;

> > +  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); 

> > + PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);  for 

> > + (Index = 0; Index < PpiListCount; Index++, PpiList++) {

> > +    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {

> > +      break;

> > +    }

> > +  }

> > +

> > +  // On MP Core Platform we must implement the ARM MP Core Info PPI 

> > + ASSERT (Index != PpiListCount);

> > +

> > +  ArmMpCoreInfoPpi = PpiList->Ppi;

> > +  ArmCoreCount = 0;

> > +  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, 

> > + &ArmCoreInfoTable);  ASSERT_EFI_ERROR (Status);

> > +

> > +  // Find the core in the ArmCoreTable  for (Index = 0; Index < 

> > + ArmCoreCount; Index++) {

> > +    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) &&

> (ArmCoreInfoTable[Index].CoreId == CoreId)) {

> > +      break;

> > +    }

> > +  }

> > +

> > +  // The ARM Core Info Table must define every core  ASSERT (Index 

> > + != ArmCoreCount);

> > +

> > +  // Clear Secondary cores MailBox

> > +  if (sizeof(UINTN) == sizeof(UINT64))

> > +    MmioWrite64 (ArmCoreInfoTable[Index].MailboxClearAddress,

> > + ArmCoreInfoTable[Index].MailboxClearValue);

> > +  else

> > +    MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,

> > + ArmCoreInfoTable[Index].MailboxClearValue);

> > +

> > +  do {

> > +    ArmCallWFI ();

> > +

> > +    // Read the Mailbox

> > +    if (sizeof(UINTN) == sizeof(UINT64))

> > +      SecondaryEntryAddr = MmioRead64

> (ArmCoreInfoTable[Index].MailboxGetAddress);

> > +    else

> > +      SecondaryEntryAddr = MmioRead32 

> > + (ArmCoreInfoTable[Index].MailboxGetAddress);

> > +

> > +    // Acknowledge the interrupt and send End of Interrupt signal.

> > +    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32

> (PcdGicInterruptInterfaceBase), &InterruptId);

> > +    // Check if it is a valid interrupt ID

> > +    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32

> (PcdGicDistributorBase))) {

> > +      // Got a valid SGI number hence signal End of Interrupt

> > +      ArmGicEndOfInterrupt (PcdGet32 

> > + (PcdGicInterruptInterfaceBase),

> AcknowledgeInterrupt);

> > +    }

> > +  } while (SecondaryEntryAddr == 0);

> > +

> > +  // Jump to secondary core entry point.

> > +  SecondaryStart = (VOID (*)())SecondaryEntryAddr;  

> > + SecondaryStart();

> > +

> > +  // The secondaries shouldn't reach here

> > +  ASSERT(FALSE);

> > +}

> > +

> > +VOID

> > +EFIAPI

> > +PrimaryMain (

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  )

> > +{

> > +  EFI_SEC_PEI_HAND_OFF        SecCoreData;

> > +  UINTN                       PpiListSize;

> > +  EFI_PEI_PPI_DESCRIPTOR      *PpiList;

> > +  UINTN                       TemporaryRamBase;

> > +  UINTN                       TemporaryRamSize;

> > +

> > +  CreatePpiList (&PpiListSize, &PpiList);

> > +

> > +  // Enable the GIC Distributor

> > +  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));

> > +

> > +  // If ArmVe has not been built as Standalone then we need to wake 

> > + up the secondary cores  if (FeaturePcdGet

> (PcdSendSgiToBringUpSecondaryCores)) {

> > +    // Sending SGI to all the Secondary CPU interfaces

> > +    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), 

> > + ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 

> > + (PcdGicSgiIntId));  }

> > +

> > +  // Adjust the Temporary Ram as the new Ppi List (Common + 

> > + Platform Ppi Lists) is created at  // the base of the primary core 

> > + stack PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT); 

> > + TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + 

> > + PpiListSize;  TemporaryRamSize = (UINTN)PcdGet32

> > + (PcdCPUCorePrimaryStackSize) - PpiListSize;

> > +

> > +  //

> > +  // Bind this information into the SEC hand-off state  // Note: 

> > + this must be in sync with the stuff in the asm file  // Note also:  

> > + HOBs (pei temp ram) MUST be above stack  //

> > +  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

> > +  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 

> > + (PcdFvBaseAddress);  SecCoreData.BootFirmwareVolumeSize =

> PcdGet32 (PcdFvSize);

> > +  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; //

> We run on the primary core (and so we use the first stack)

> > +  SecCoreData.TemporaryRamSize       = TemporaryRamSize;

> > +  SecCoreData.PeiTemporaryRamBase    =

> SecCoreData.TemporaryRamBase;

> > +  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE

> (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);

> > +  SecCoreData.StackBase              = (VOID

> *)((UINTN)SecCoreData.TemporaryRamBase + 

> SecCoreData.PeiTemporaryRamSize);

> > +  SecCoreData.StackSize              = (TemporaryRamBase +

> TemporaryRamSize) - (UINTN)SecCoreData.StackBase;

> > +

> > +  // Jump to PEI core entry point

> > +  PeiCoreEntryPoint (&SecCoreData, PpiList); }

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.c

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.c

> > new file mode 100644

> > index 0000000..7b45c00

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCore.c

> > @@ -0,0 +1,149 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World 

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions 

> > +of the BSD License

> > +*  which accompanies this distribution.  The full text of the 

> > +license may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/PrePeiCore.c

> > +

> > +**/

> > +

> > +#include <Library/BaseLib.h>

> > +#include <Library/DebugAgentLib.h>

> > +#include <Library/ArmLib.h>

> > +

> > +#include "PrePeiCore.h"

> > +

> > +CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI

> mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };

> > +

> > +CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {

> > +  {

> > +    EFI_PEI_PPI_DESCRIPTOR_PPI,

> > +    &gEfiTemporaryRamSupportPpiGuid,

> > +    (VOID *) &mTemporaryRamSupportPpi

> > +  }

> > +};

> > +

> > +VOID

> > +CreatePpiList (

> > +  OUT UINTN                   *PpiListSize,

> > +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList

> > +  )

> > +{

> > +  EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;

> > +  UINTN                   PlatformPpiListSize;

> > +  UINTN                   ListBase;

> > +  EFI_PEI_PPI_DESCRIPTOR *LastPpi;

> > +

> > +  // Get the Platform PPIs

> > +  PlatformPpiListSize = 0;

> > +  ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, 

> > + &PlatformPpiList);

> > +

> > +  // Copy the Common and Platform PPis in Temporrary Memory  

> > + ListBase = PcdGet64 (PcdCPUCoresStackBase);  CopyMem 

> > + ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));  

> > + CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), 

> > + PlatformPpiList, PlatformPpiListSize);

> > +

> > +  // Set the Terminate flag on the last PPI entry  LastPpi = 

> > + (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) +

> > + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;

> > + LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

> > +

> > +  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;

> > +  *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize; }

> > +

> > +VOID

> > +CEntryPoint (

> > +  IN  UINTN                     MpId,

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  )

> > +{

> > +  // Data Cache enabled on Primary core when MMU is enabled.

> > +  ArmDisableDataCache ();

> > +  // Invalidate Data cache

> > +  ArmInvalidateDataCache ();

> > +  // Invalidate instruction cache

> > +  ArmInvalidateInstructionCache ();

> > +  // Enable Instruction Caches on all cores.

> > +  ArmEnableInstructionCache ();

> > +

> > +  //

> > +  // Note: Doesn't have to Enable CPU interface in non-secure 

> > + world, // as Non-secure interface is already enabled in Secure world.

> > +  //

> > +

> > +  // Write VBAR - The Exception Vector table must be aligned to its 

> > + requirement  // Note: The AArch64 Vector table must be 2k-byte 

> > + aligned - if this assertion fails ensure  // 'Align=4K' is defined 

> > + into your FDF

> for this module.

> > +  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT)

> == 0);

> > + ArmWriteVBar ((UINTN)PeiVectorTable);

> > +

> > +  //Note: The MMU will be enabled by MemoryPeim. Only the primary

> core will have the MMU on.

> > +

> > +  // If not primary Jump to Secondary Main  if 

> > + (ArmPlatformIsPrimaryCore (MpId)) {

> > +    // Initialize the Debug Agent for Source Level Debugging

> > +    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL,

> NULL);

> > +    SaveAndSetDebugTimerInterrupt (TRUE);

> > +

> > +    // Initialize the platform specific controllers

> > +    ArmPlatformInitialize (MpId);

> > +

> > +    // Goto primary Main.

> > +    PrimaryMain (PeiCoreEntryPoint);  } else {

> > +    SecondaryMain (MpId);

> > +  }

> > +

> > +  // PEI Core should always load and never return

> > +  ASSERT (FALSE);

> > +}

> > +

> > +EFI_STATUS

> > +EFIAPI

> > +PrePeiCoreTemporaryRamSupport (

> > +  IN CONST EFI_PEI_SERVICES   **PeiServices,

> > +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

> > +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

> > +  IN UINTN                    CopySize

> > +  )

> > +{

> > +  VOID                             *OldHeap;

> > +  VOID                             *NewHeap;

> > +  VOID                             *OldStack;

> > +  VOID                             *NewStack;

> > +  UINTN                            HeapSize;

> > +

> > +  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);

> > +

> > +  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;

> > +  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - 

> > + HeapSize));

> > +

> > +  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); 

> > + NewStack = (VOID*)(UINTN)PermanentMemoryBase;

> > +

> > +  //

> > +  // Migrate the temporary memory stack to permanent memory stack.

> > +  //

> > +  CopyMem (NewStack, OldStack, CopySize - HeapSize);

> > +

> > +  //

> > +  // Migrate the temporary memory heap to permanent memory heap.

> > +  //

> > +  CopyMem (NewHeap, OldHeap, HeapSize);

> > +

> > +  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);

> > +

> > +  return EFI_SUCCESS;

> > +}

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.h

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCore.h

> > new file mode 100644

> > index 0000000..334f086

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCore.h

> > @@ -0,0 +1,85 @@

> > +/** @file

> > +*  Main file supporting the transition to PEI Core in Normal World 

> > +for Versatile Express

> > +*

> > +*  Copyright (c) 2011, ARM Limited. All rights reserved.

> > +*  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +*

> > +*  This program and the accompanying materials

> > +*  are licensed and made available under the terms and conditions 

> > +of the BSD License

> > +*  which accompanies this distribution.  The full text of the 

> > +license may be found at

> > +*  http://opensource.org/licenses/bsd-license.php

> > +*

> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS,

> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

> EXPRESS OR IMPLIED.

> > +*

> > +**/

> > +/**

> > +  Unmodified from:

> > +   ArmPlatformPkg/PrePeiCore/PrePeiCore.h

> > +

> > +**/

> > +

> > +#ifndef __PREPEICORE_H_

> > +#define __PREPEICORE_H_

> > +

> > +#include <Library/ArmLib.h>

> > +#include <Library/ArmPlatformLib.h> #include 

> > +<Library/BaseMemoryLib.h> #include <Library/DebugLib.h> #include 

> > +<Library/IoLib.h> #include <Library/PcdLib.h>

> > +

> > +#include <PiPei.h>

> > +#include <Ppi/TemporaryRamSupport.h>

> > +

> > +VOID

> > +CreatePpiList (

> > +  OUT UINTN                   *PpiListSize,

> > +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList

> > +  );

> > +

> > +EFI_STATUS

> > +EFIAPI

> > +PrePeiCoreTemporaryRamSupport (

> > +  IN CONST EFI_PEI_SERVICES   **PeiServices,

> > +  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

> > +  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

> > +  IN UINTN                    CopySize

> > +  );

> > +

> > +VOID

> > +SecSwitchStack (

> > +  INTN    StackDelta

> > +  );

> > +

> > +// Vector Table for Pei Phase

> > +VOID  PeiVectorTable (VOID);

> > +

> > +VOID

> > +EFIAPI

> > +PrimaryMain (

> > +  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

> > +  );

> > +

> > +/*

> > + * This is the main function for secondary cores. They loop around 

> > +until a non Null value is written to

> > + * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

> > + * Note:The secondary cores, while executing secondary_main, 

> > +assumes

> that:

> > + *      : SGI 0 is configured as Non-secure interrupt

> > + *      : Priority Mask is configured to allow SGI 0

> > + *      : Interrupt Distributor and CPU interfaces are enabled

> > + *

> > + */

> > +VOID

> > +EFIAPI

> > +SecondaryMain (

> > +  IN UINTN MpId

> > +  );

> > +

> > +VOID

> > +PeiCommonExceptionEntry (

> > +  IN UINT32 Entry,

> > +  IN UINTN LR

> > +  );

> > +

> > +#endif

> > diff --git

> >

> a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCoreMPCore.inf

> >

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiC

> ore

> > /PrePeiCoreMPCore.inf

> > new file mode 100644

> > index 0000000..28b5b04

> > --- /dev/null

> > +++

> b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePei

> > +++ Core/PrePeiCoreMPCore.inf

> > @@ -0,0 +1,76 @@

> > +#/** @file

> > +#  Pre PeiCore - Hand-off to PEI Core in Normal World # #  

> > +Copyright

> > +(c) 2011-2014, ARM Limited. All rights reserved.

> > +#  Copyright (c) 2016, AMD Inc. All rights reserved.

> > +#

> > +#  This program and the accompanying materials #  are licensed and 

> > +made available under the terms and conditions of the BSD License # 

> > +which accompanies this distribution.  The full text of the license 

> > +may be found at #  http://opensource.org/licenses/bsd-license.php

> > +#

> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"

> > +BASIS, #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,

> EITHER EXPRESS OR IMPLIED.

> > +#

> > +#**/

> > +#/**

> > +#  Derived from:

> > +#   ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

> > +#

> > +#  Removes [Sources.ARM] section

> > +#

> > +#**/

> > +

> > +[Defines]

> > +  INF_VERSION                    = 0x00010005

> > +  BASE_NAME                      = ArmPlatformPrePeiCore

> > +  FILE_GUID                      = 469fc080-aec1-11df-927c-0002a5d5c51b

> > +  MODULE_TYPE                    = SEC

> > +  VERSION_STRING                 = 1.0

> > +

> > +[Sources.common]

> > +  MainMPCore.c

> > +  PrePeiCore.c

> > +

> > +[Sources.AARCH64]

> > +  AArch64/ArchPrePeiCore.c

> > +  AArch64/PrePeiCoreEntryPoint.S

> > +  AArch64/SwitchStack.S

> > +  AArch64/Exception.S

> > +  AArch64/Helper.S

> > +

> > +[Packages]

> > +  MdePkg/MdePkg.dec

> > +  MdeModulePkg/MdeModulePkg.dec

> > +  ArmPkg/ArmPkg.dec

> > +  ArmPlatformPkg/ArmPlatformPkg.dec

> > +

> > +[LibraryClasses]

> > +  ArmLib

> > +  ArmPlatformLib

> > +  BaseLib

> > +  DebugLib

> > +  DebugAgentLib

> > +  IoLib

> > +  ArmGicLib

> > +  PrintLib

> > +  SerialPortLib

> > +

> > +[Ppis]

> > +  gEfiTemporaryRamSupportPpiGuid

> > +  gArmMpCoreInfoPpiGuid

> > +

> > +[FeaturePcd]

> > +  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores

> > +

> > +[FixedPcd]

> > +  gArmTokenSpaceGuid.PcdFvBaseAddress

> > +  gArmTokenSpaceGuid.PcdFvSize

> > +

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize

> > +  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize

> > +

> > +  gArmTokenSpaceGuid.PcdGicDistributorBase

> > +  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

> > +  gArmTokenSpaceGuid.PcdGicSgiIntId

> > --

> > 1.9.1

> >
Ard Biesheuvel May 2, 2016, 6:43 a.m. | #4
On 2 May 2016 at 00:27, Duran, Leo <leo.duran@amd.com> wrote:
> Actually, I probably should have said:
> Considering that ARM_CORE_INFO defines MailboxClearValue as UINT64, it seems reasonable to allow 64-bit MMMIO access.
>

I spent some time looking into this.

The EFI_PHYSICAL_ADDRESS field in ARM_CORE_INFO is the size of the
*address* of the mailbox register, not the size of the register
itself.
However, I think it is reasonable to stipulate that mailbox registers
are at least native word size, and the type of the MailboxClearValue
field already suggests that.

So what I propose is to:
- remove MPCore functionality from Juno and FVP, since they are the
only ones that use a 32-bit mailbox register on a 64-bit arch
- retype MailboxClearValue as UINTN, and update the related code accordingly
- remove the code that installs an mpcore configuration table that is
consumed by the linuxloader
- implement an ACPI parking protocol DXE

I am not sure whether we are interested in having code upstream that
manipulates the DT cpu nodes to assign the mailbox addresses. I think
for now, ACPI support is sufficient and we can look into DT when
anyone asks for it.

Patch

diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
index e83a8ef..6ee7181 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
@@ -561,7 +561,7 @@  DEFINE TRANS_CODE = $(EL3_TO_EL2)
 !if $(DO_PSCI)
   ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
 !else
-  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
 !endif
   MdeModulePkg/Core/Pei/PeiMain.inf
   MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
index cbfb6c3..0134af2 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
@@ -250,7 +250,7 @@  READ_LOCK_STATUS   = TRUE
 !if $(DO_PSCI)
   INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
 !else
-  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
 !endif
   INF MdeModulePkg/Core/Pei/PeiMain.inf
   INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
new file mode 100644
index 0000000..9f86d3e
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
@@ -0,0 +1,58 @@ 
+/** @file
+*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
+*
+*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, AMD Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/** 
+  Unmodified from:
+   ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
+
+**/
+
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "PrePeiCore.h"
+
+VOID
+PeiCommonExceptionEntry (
+  IN UINT32 Entry,
+  IN UINTN LR
+  )
+{
+  CHAR8           Buffer[100];
+  UINTN           CharCount;
+
+  switch (Entry) {
+  case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:
+    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR);
+    break;
+  case EXCEPT_AARCH64_IRQ:
+    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR);
+    break;
+  case EXCEPT_AARCH64_FIQ:
+    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR);
+    break;
+  case EXCEPT_AARCH64_SERROR:
+    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR);
+    break;
+  default:
+    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR);
+    break;
+  }
+
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  while(1);
+}
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
new file mode 100644
index 0000000..38a4257
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
@@ -0,0 +1,126 @@ 
+#
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2016, AMD Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#/**
+#  Unmodified from:
+#   ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
+#
+#**/
+
+#include <Chipset/AArch64.h>
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+.text
+
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+#define TO_HANDLER                                              \
+   EL1_OR_EL2(x1)                                               \
+1: mrs  x1, elr_el1    /* EL1 Exception Link Register */       ;\
+   b    3f                                                     ;\
+2: mrs  x1, elr_el2    /* EL2 Exception Link Register */       ;\
+3: bl   ASM_PFX(PeiCommonExceptionEntry)                       ;
+
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+
+VECTOR_BASE(PeiVectorTable)
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
+_DefaultSyncExceptHandler_t:
+  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
+_DefaultIrq_t:
+  mov  x0, #EXCEPT_AARCH64_IRQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
+_DefaultFiq_t:
+  mov  x0, #EXCEPT_AARCH64_FIQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
+_DefaultSError_t:
+  mov  x0, #EXCEPT_AARCH64_SERROR
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
+_DefaultSyncExceptHandler_h:
+  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
+_DefaultIrq_h:
+  mov  x0, #EXCEPT_AARCH64_IRQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
+_DefaultFiq_h:
+  mov  x0, #EXCEPT_AARCH64_FIQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
+_DefaultSError_h:
+  mov  x0, #EXCEPT_AARCH64_SERROR
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
+_DefaultSyncExceptHandler_LowerA64:
+  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
+_DefaultIrq_LowerA64:
+  mov  x0, #EXCEPT_AARCH64_IRQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
+_DefaultFiq_LowerA64:
+  mov  x0, #EXCEPT_AARCH64_FIQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
+_DefaultSError_LowerA64:
+  mov  x0, #EXCEPT_AARCH64_SERROR
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
+_DefaultSyncExceptHandler_LowerA32:
+  mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
+_DefaultIrq_LowerA32:
+  mov  x0, #EXCEPT_AARCH64_IRQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
+_DefaultFiq_LowerA32:
+  mov  x0, #EXCEPT_AARCH64_FIQ
+  TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
+_DefaultSError_LowerA32:
+  mov  x0, #EXCEPT_AARCH64_SERROR
+  TO_HANDLER
+
+VECTOR_END(PeiVectorTable)
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
new file mode 100644
index 0000000..b9a0049
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
@@ -0,0 +1,54 @@ 
+#========================================================================================
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#  Copyright (c) 2016, AMD Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http:#opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#=======================================================================================
+#/**
+#  Unmodified from:
+#   ArmPlatformPkg/PrePeiCore/AArch64/Helper.S
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
+
+#start of the code section
+.text
+.align 3
+
+GCC_ASM_EXPORT(SetupExceptionLevel1)
+GCC_ASM_EXPORT(SetupExceptionLevel2)
+
+// Setup EL1 while in EL1
+ASM_PFX(SetupExceptionLevel1):
+   mov  x5, x30                   // Save LR
+
+   mov  x0, #CPACR_CP_FULL_ACCESS
+   bl   ASM_PFX(ArmWriteCpacr)    // Disable copro traps to EL1
+
+   ret  x5
+
+// Setup EL2 while in EL2
+ASM_PFX(SetupExceptionLevel2):
+   msr     sctlr_el2, xzr
+   mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register
+
+   // Send all interrupts to their respective Exception levels for EL2
+   orr     x0, x0, #(1 << 3)      // Enable EL2 FIQ
+   orr     x0, x0, #(1 << 4)      // Enable EL2 IRQ
+   orr     x0, x0, #(1 << 5)      // Enable EL2 SError and Abort
+   msr     hcr_el2, x0            // Write back our settings
+
+   msr     cptr_el2, xzr          // Disable copro traps to EL2
+
+   ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
new file mode 100644
index 0000000..2ddf4d4
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
@@ -0,0 +1,112 @@ 
+//
+//  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+//  Copyright (c) 2016, AMD Inc. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#/**
+#  Unmodified from:
+#   ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_IMPORT(CEntryPoint)
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_IMPORT(ArmReadMpidr)
+GCC_ASM_IMPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(_ModuleEntryPoint)
+
+StartupAddr: .8byte CEntryPoint
+
+ASM_PFX(_ModuleEntryPoint):
+  // Do early platform specific actions
+  bl    ASM_PFX(ArmPlatformPeiBootAction)
+
+// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
+//       and configure the system accordingly. EL2 is default if possible.
+// If we started in EL3 we need to switch and run at EL2.
+// If we are running at EL2 stay in EL2
+// If we are starting at EL1 stay in EL1.
+
+// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
+// If started at EL1 or EL2 Sec jumps directly to PEI without making any
+// changes.
+
+// Which EL are we running at? Every EL needs some level of setup...
+// We should not run this code in EL3
+  EL1_OR_EL2(x0)
+1:bl    ASM_PFX(SetupExceptionLevel1)
+  b     ASM_PFX(MainEntryPoint)
+2:bl    ASM_PFX(SetupExceptionLevel2)
+  b     ASM_PFX(MainEntryPoint)
+
+ASM_PFX(MainEntryPoint):
+  // Identify CPU ID
+  bl    ASM_PFX(ArmReadMpidr)
+  // Keep a copy of the MpId register value
+  mov   x5, x0
+
+  // Is it the Primary Core ?
+  bl    ASM_PFX(ArmPlatformIsPrimaryCore)
+
+  // Get the top of the primary stacks (and the base of the secondary stacks)
+  LoadConstantToReg (FixedPcdGet64(PcdCPUCoresStackBase), x1)
+  LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)
+  add   x1, x1, x2
+
+  // x0 is equal to 1 if I am the primary core
+  cmp   x0, #1
+  b.eq   _SetupPrimaryCoreStack
+
+_SetupSecondaryCoreStack:
+  // x1 contains the base of the secondary stacks
+
+  // Get the Core Position
+  mov   x6, x1      // Save base of the secondary stacks
+  mov   x0, x5
+  bl    ASM_PFX(ArmPlatformGetCorePosition)
+  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
+  add   x0, x0, #1
+
+  // StackOffset = CorePos * StackSize
+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)
+  mul   x0, x0, x2
+  // SP = StackBase + StackOffset
+  add   sp, x6, x0
+
+_PrepareArguments:
+  // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
+  LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)
+  add   x2, x2, #8
+  ldr   x1, [x2]
+
+  // Move sec startup address into a data register
+  // Ensure we're jumping to FV version of the code (not boot remapped alias)
+  ldr   x3, StartupAddr
+
+  // Jump to PrePeiCore C code
+  //    x0 = mp_id
+  //    x1 = pei_core_address
+  mov   x0, x5
+  blr   x3
+
+_SetupPrimaryCoreStack:
+  mov   sp, x1
+  b     _PrepareArguments
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
new file mode 100644
index 0000000..8414d29
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
@@ -0,0 +1,49 @@ 
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+#/**
+#  Unmodified from:
+#   ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S
+#
+#**/
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(SecSwitchStack)
+
+
+
+#/**
+#  This allows the caller to switch the stack and return
+#
+# @param      StackDelta     Signed amount by which to modify the stack pointer
+#
+# @return     Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#SecSwitchStack (
+#  VOID  *StackDelta
+#  )#
+#
+ASM_PFX(SecSwitchStack):
+    mov   x1, sp
+    add   x1, x0, x1
+    mov   sp, x1
+    ret
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
new file mode 100644
index 0000000..c708f84
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -0,0 +1,168 @@ 
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, AMD Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/** 
+  Derived from:
+   ArmPlatformPkg/PrePeiCore/MainMPCore.c
+
+  Adds MmioWrite64() for 64-bit mailbox pointers.
+
+**/
+
+#include <Library/ArmGicLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include "PrePeiCore.h"
+
+/*
+ * This is the main function for secondary cores. They loop around until a non Null value is written to
+ * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
+ * Note:The secondary cores, while executing secondary_main, assumes that:
+ *      : SGI 0 is configured as Non-secure interrupt
+ *      : Priority Mask is configured to allow SGI 0
+ *      : Interrupt Distributor and CPU interfaces are enabled
+ *
+ */
+VOID
+EFIAPI
+SecondaryMain (
+  IN UINTN MpId
+  )
+{
+  EFI_STATUS              Status;
+  UINTN                   PpiListSize;
+  UINTN                   PpiListCount;
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;
+  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
+  UINTN                   Index;
+  UINTN                   ArmCoreCount;
+  ARM_CORE_INFO           *ArmCoreInfoTable;
+  UINT32                  ClusterId;
+  UINT32                  CoreId;
+  VOID                    (*SecondaryStart)(VOID);
+  UINTN                   SecondaryEntryAddr;
+  UINTN                   AcknowledgeInterrupt;
+  UINTN                   InterruptId;
+
+  ClusterId = GET_CLUSTER_ID(MpId);
+  CoreId    = GET_CORE_ID(MpId);
+
+  // Get the gArmMpCoreInfoPpiGuid
+  PpiListSize = 0;
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
+  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
+    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
+      break;
+    }
+  }
+
+  // On MP Core Platform we must implement the ARM MP Core Info PPI
+  ASSERT (Index != PpiListCount);
+
+  ArmMpCoreInfoPpi = PpiList->Ppi;
+  ArmCoreCount = 0;
+  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+  ASSERT_EFI_ERROR (Status);
+
+  // Find the core in the ArmCoreTable
+  for (Index = 0; Index < ArmCoreCount; Index++) {
+    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
+      break;
+    }
+  }
+
+  // The ARM Core Info Table must define every core
+  ASSERT (Index != ArmCoreCount);
+
+  // Clear Secondary cores MailBox
+  if (sizeof(UINTN) == sizeof(UINT64))
+    MmioWrite64 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
+  else
+    MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
+
+  do {
+    ArmCallWFI ();
+
+    // Read the Mailbox
+    if (sizeof(UINTN) == sizeof(UINT64))
+      SecondaryEntryAddr = MmioRead64 (ArmCoreInfoTable[Index].MailboxGetAddress);
+    else
+      SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
+
+    // Acknowledge the interrupt and send End of Interrupt signal.
+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);
+    // Check if it is a valid interrupt ID
+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
+      // Got a valid SGI number hence signal End of Interrupt
+      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
+    }
+  } while (SecondaryEntryAddr == 0);
+
+  // Jump to secondary core entry point.
+  SecondaryStart = (VOID (*)())SecondaryEntryAddr;
+  SecondaryStart();
+
+  // The secondaries shouldn't reach here
+  ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+PrimaryMain (
+  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
+  )
+{
+  EFI_SEC_PEI_HAND_OFF        SecCoreData;
+  UINTN                       PpiListSize;
+  EFI_PEI_PPI_DESCRIPTOR      *PpiList;
+  UINTN                       TemporaryRamBase;
+  UINTN                       TemporaryRamSize;
+
+  CreatePpiList (&PpiListSize, &PpiList);
+
+  // Enable the GIC Distributor
+  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+
+  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
+  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
+    // Sending SGI to all the Secondary CPU interfaces
+    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
+  }
+
+  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
+  // the base of the primary core stack
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
+  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
+  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
+
+  //
+  // Bind this information into the SEC hand-off state
+  // Note: this must be in sync with the stuff in the asm file
+  // Note also:  HOBs (pei temp ram) MUST be above stack
+  //
+  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
+  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
+  SecCoreData.TemporaryRamSize       = TemporaryRamSize;
+  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
+  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
+  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
+
+  // Jump to PEI core entry point
+  PeiCoreEntryPoint (&SecCoreData, PpiList);
+}
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
new file mode 100644
index 0000000..7b45c00
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -0,0 +1,149 @@ 
+/** @file
+*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, AMD Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/** 
+  Unmodified from:
+   ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/ArmLib.h>
+
+#include "PrePeiCore.h"
+
+CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI   mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
+
+CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gEfiTemporaryRamSupportPpiGuid,
+    (VOID *) &mTemporaryRamSupportPpi
+  }
+};
+
+VOID
+CreatePpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
+  UINTN                   PlatformPpiListSize;
+  UINTN                   ListBase;
+  EFI_PEI_PPI_DESCRIPTOR *LastPpi;
+
+  // Get the Platform PPIs
+  PlatformPpiListSize = 0;
+  ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
+
+  // Copy the Common and Platform PPis in Temporrary Memory
+  ListBase = PcdGet64 (PcdCPUCoresStackBase);
+  CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));
+  CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
+
+  // Set the Terminate flag on the last PPI entry
+  LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;
+  LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+
+  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;
+  *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;
+}
+
+VOID
+CEntryPoint (
+  IN  UINTN                     MpId,
+  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
+  )
+{
+  // Data Cache enabled on Primary core when MMU is enabled.
+  ArmDisableDataCache ();
+  // Invalidate Data cache
+  ArmInvalidateDataCache ();
+  // Invalidate instruction cache
+  ArmInvalidateInstructionCache ();
+  // Enable Instruction Caches on all cores.
+  ArmEnableInstructionCache ();
+
+  //
+  // Note: Doesn't have to Enable CPU interface in non-secure world,
+  // as Non-secure interface is already enabled in Secure world.
+  //
+
+  // Write VBAR - The Exception Vector table must be aligned to its requirement
+  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
+  // 'Align=4K' is defined into your FDF for this module.
+  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+  ArmWriteVBar ((UINTN)PeiVectorTable);
+
+  //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
+
+  // If not primary Jump to Secondary Main
+  if (ArmPlatformIsPrimaryCore (MpId)) {
+    // Initialize the Debug Agent for Source Level Debugging
+    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+    SaveAndSetDebugTimerInterrupt (TRUE);
+
+    // Initialize the platform specific controllers
+    ArmPlatformInitialize (MpId);
+
+    // Goto primary Main.
+    PrimaryMain (PeiCoreEntryPoint);
+  } else {
+    SecondaryMain (MpId);
+  }
+
+  // PEI Core should always load and never return
+  ASSERT (FALSE);
+}
+
+EFI_STATUS
+EFIAPI
+PrePeiCoreTemporaryRamSupport (
+  IN CONST EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
+  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
+  IN UINTN                    CopySize
+  )
+{
+  VOID                             *OldHeap;
+  VOID                             *NewHeap;
+  VOID                             *OldStack;
+  VOID                             *NewStack;
+  UINTN                            HeapSize;
+
+  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
+
+  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
+
+  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
+  NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+  //
+  // Migrate the temporary memory stack to permanent memory stack.
+  //
+  CopyMem (NewStack, OldStack, CopySize - HeapSize);
+
+  //
+  // Migrate the temporary memory heap to permanent memory heap.
+  //
+  CopyMem (NewHeap, OldHeap, HeapSize);
+
+  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
new file mode 100644
index 0000000..334f086
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
@@ -0,0 +1,85 @@ 
+/** @file
+*  Main file supporting the transition to PEI Core in Normal World for Versatile Express
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, AMD Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/** 
+  Unmodified from:
+   ArmPlatformPkg/PrePeiCore/PrePeiCore.h
+
+**/
+
+#ifndef __PREPEICORE_H_
+#define __PREPEICORE_H_
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <PiPei.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+VOID
+CreatePpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  );
+
+EFI_STATUS
+EFIAPI
+PrePeiCoreTemporaryRamSupport (
+  IN CONST EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
+  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
+  IN UINTN                    CopySize
+  );
+
+VOID
+SecSwitchStack (
+  INTN    StackDelta
+  );
+
+// Vector Table for Pei Phase
+VOID  PeiVectorTable (VOID);
+
+VOID
+EFIAPI
+PrimaryMain (
+  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
+  );
+
+/*
+ * This is the main function for secondary cores. They loop around until a non Null value is written to
+ * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
+ * Note:The secondary cores, while executing secondary_main, assumes that:
+ *      : SGI 0 is configured as Non-secure interrupt
+ *      : Priority Mask is configured to allow SGI 0
+ *      : Interrupt Distributor and CPU interfaces are enabled
+ *
+ */
+VOID
+EFIAPI
+SecondaryMain (
+  IN UINTN MpId
+  );
+
+VOID
+PeiCommonExceptionEntry (
+  IN UINT32 Entry,
+  IN UINTN LR
+  );
+
+#endif
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
new file mode 100644
index 0000000..28b5b04
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -0,0 +1,76 @@ 
+#/** @file
+#  Pre PeiCore - Hand-off to PEI Core in Normal World
+#
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2016, AMD Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+#
+#  Removes [Sources.ARM] section
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmPlatformPrePeiCore
+  FILE_GUID                      = 469fc080-aec1-11df-927c-0002a5d5c51b
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.0
+
+[Sources.common]
+  MainMPCore.c
+  PrePeiCore.c
+
+[Sources.AARCH64]
+  AArch64/ArchPrePeiCore.c
+  AArch64/PrePeiCoreEntryPoint.S
+  AArch64/SwitchStack.S
+  AArch64/Exception.S
+  AArch64/Helper.S
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmPlatformLib
+  BaseLib
+  DebugLib
+  DebugAgentLib
+  IoLib
+  ArmGicLib
+  PrintLib
+  SerialPortLib
+
+[Ppis]
+  gEfiTemporaryRamSupportPpiGuid
+  gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdFvSize
+
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicSgiIntId