[Linaro-uefi,RFC,5/7] Platforms/Styx/PlatInitPei: don't bring up secondaries in PEI

Message ID 1462196143-21998-6-git-send-email-ard.biesheuvel@linaro.org
State New
Headers show

Commit Message

Ard Biesheuvel May 2, 2016, 1:35 p.m.
The ARM MpCore implementation is intended for environments where all
cores enter UEFI straight out of reset. In this case, we need an early
secondary code path that pens up the secondaries until we are ready to
release them.

For Styx, we either invoke the SCP or the EL3 firmware explicitly to
release the cores into PEI, only to park them until the time we are
ready to put them in the pen where the OS can pick them up.

Since the ARM MpCore code is fragile and unmaintained (due to the fact
that ARM prefers PSCI as the MP startup implementation), let's not use
it if we don't have to.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c   | 209 +-------------------
 Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.h   |   4 -
 Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf |   3 -
 3 files changed, 3 insertions(+), 213 deletions(-)

Patch

diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
index a1f6cabee901..ed6c67fed38f 100644
--- a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
+++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
@@ -14,8 +14,6 @@ 
 
 #include "PlatInitPei.h"
 
-#define PLATINIT_CONTEXT_ID       ( 0x0 )   // used on SMC calls
-
 /*----------------------------------------------------------------------------------------
  *                                  G L O B A L S
  *----------------------------------------------------------------------------------------
@@ -23,107 +21,50 @@ 
 //
 // CoreInfo table
 //
-ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
+STATIC ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
   {
     // Cluster 0, Core 0
     0x0, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 0, Core 1
     0x0, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 1, Core 0
     0x1, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 1, Core 1
     0x1, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 2, Core 0
     0x2, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 2, Core 1
     0x2, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 3, Core 0
     0x3, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   },
   {
     // Cluster 3, Core 1
     0x3, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (EFI_PHYSICAL_ADDRESS)0,
-    (UINT64)0x0
   }
 };
 
 //
 // Core count
 //
-UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
-
-//
-// Adding an extra entry to make sure Mailbox is UINTN-aligned
-// 
-UINTN mMailboxTable[NUM_CORES + 1] = { 0 };
-
+STATIC UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
 
 /*----------------------------------------------------------------------------------------
  *                                  E X T E R N S
  *----------------------------------------------------------------------------------------
  */
-extern EFI_GUID gPeiIscpPpiGuid;
-extern EFI_GUID gAmdStyxPlatInitPpiGuid;
-
 UINTN
 ArmGetCpuCountPerCluster (
   VOID
@@ -131,23 +72,10 @@  ArmGetCpuCountPerCluster (
 
 
 /*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-EFI_STATUS
-EFIAPI    
-PlatInitEndOfPeiPpiCallback (
-  IN CONST EFI_PEI_SERVICES     **PeiServices,
-  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
-  IN VOID                       *Ppi
-  );
-
-
-/*----------------------------------------------------------------------------------------
  *                                   P P I   L I S T
  *----------------------------------------------------------------------------------------
  */
-EFI_PEI_ISCP_PPI            *PeiIscpPpi;
+STATIC EFI_PEI_ISCP_PPI            *PeiIscpPpi;
 
 
 /*----------------------------------------------------------------------------------------
@@ -161,13 +89,6 @@  STATIC EFI_PEI_PPI_DESCRIPTOR mPlatInitPpiDescriptor =
   NULL
 };
 
-STATIC EFI_PEI_NOTIFY_DESCRIPTOR mPlatInitNotifyDescriptor =
-{
-  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
-  &gEfiEndOfPeiSignalPpiGuid,
-  (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatInitEndOfPeiPpiCallback
-};
-
 
 /**
  *---------------------------------------------------------------------------------------
@@ -200,7 +121,6 @@  PlatInitPeiEntryPoint (
   ISCP_CPU_RESET_INFO         CpuResetInfo = {0};
   ISCP_MAC_INFO               MacAddrInfo = {0};
   UINT64                      MacAddr0, MacAddr1;
-  UINTN                       MailboxBase;
   UINTN                       CpuCoreCount, CpuMap, CpuMapSize;
   UINTN                       Index, CoreNum;
   UINT32                      *CpuIdReg = (UINT32 *)FixedPcdGet32 (PcdCpuIdRegister);
@@ -244,12 +164,6 @@  PlatInitPeiEntryPoint (
   if (!FixedPcdGetBool (PcdIscpSupport)) {
     DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n"));
   } else {
-    // Make sure Mailbox is UINTN aligned
-    MailboxBase = (UINTN)&mMailboxTable[0];
-    if (MailboxBase % sizeof(MailboxBase) != 0) {
-      MailboxBase += sizeof(MailboxBase) - MailboxBase % sizeof(MailboxBase);
-    }
-
     //
     // Walk CPU map to enumerate active cores
     // 
@@ -265,12 +179,6 @@  PlatInitPeiEntryPoint (
         mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
         mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
 
-        mAmdMpCoreInfoTable[Index].MailboxSetAddress = MailboxBase;
-        mAmdMpCoreInfoTable[Index].MailboxGetAddress = MailboxBase;
-        mAmdMpCoreInfoTable[Index].MailboxClearAddress = MailboxBase;
-        mAmdMpCoreInfoTable[Index].MailboxClearValue = 0;
-        MailboxBase += sizeof(MailboxBase);
-
         DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d   CoreId = %d\n",
           Index, mAmdMpCoreInfoTable[Index].ClusterId,
           mAmdMpCoreInfoTable[Index].CoreId));
@@ -332,12 +240,6 @@  PlatInitPeiEntryPoint (
   DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA)));
   DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB)));
 
-  // If the OS can't launch secondary cores, hook callback for end of PEI phase
-  if (!FixedPcdGetBool (PcdPsciOsSupport)) {
-    Status = (*PeiServices)->NotifyPpi(PeiServices, &mPlatInitNotifyDescriptor);
-    ASSERT_EFI_ERROR (Status);
-  }
-
   // Let other PEI modules know we're done!
   Status = (*PeiServices)->InstallPpi (PeiServices, &mPlatInitPpiDescriptor);
   ASSERT_EFI_ERROR (Status);
@@ -345,108 +247,3 @@  PlatInitPeiEntryPoint (
   return Status;
 }
 
-
-/**
-  PEI termination callback.
-
-  @param PeiServices         General purpose services available to every PEIM.
-  @param NotifyDescriptor    Not used.
-  @param Ppi                 Not used.
-
-  @retval EFI_SUCCESS        If the interface could be successfully
-                             installed.
-
-**/
-EFI_STATUS
-EFIAPI    
-PlatInitEndOfPeiPpiCallback (
-  IN CONST EFI_PEI_SERVICES     **PeiServices,
-  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
-  IN VOID                       *Ppi
-  )
-{
-  EFI_STATUS                  Status = EFI_SUCCESS;
-  ISCP_CPU_RESET_INFO         CpuResetInfo = {0};
-  BOOLEAN                     fCoreTransitionDone;
-  ARM_SMC_ARGS                SmcRegs;
-  UINTN                       Index;
-
-  DEBUG ((EFI_D_ERROR, "PlatInit: END_OF_PEI\n"));
-
-  //
-  // Launch secondary cores to the UEFI pen.
-  //
-  // The cores will land at the SecondaryMain() entry point in either of:
-  //  1) ArmPlatfromPkg/PrePiCore/MainMPCore.c
-  //  2) ArmPlatfromPkg/PrePi/MainMPCore.c
-  // From there, the cores will jump to the OS (via FDT's spin-table)
-  // or to another UEFI pen that supports the MP-Parking protocol.
-  //
-  if (FixedPcdGetBool (PcdTrustedFWSupport)) {
-    for (Index = 0; Index < mAmdCoreCount; ++Index) {
-      SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64;
-      SmcRegs.Arg1 = GET_MPID (mAmdMpCoreInfoTable[Index].ClusterId,
-                               mAmdMpCoreInfoTable[Index].CoreId);
-      SmcRegs.Arg2 = FixedPcdGet64 (PcdUefiEntryAddress);
-      SmcRegs.Arg3 = PLATINIT_CONTEXT_ID;
-      ArmCallSmc (&SmcRegs);
-
-      if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS ||
-          SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) {
-        DEBUG ((EFI_D_ERROR, "Core[%d] at RUN state.\n", Index));
-      } else {
-        DEBUG ((EFI_D_ERROR, "Warning: Could not transition Core[%d] to RUN state.\n", Index));
-      }
-    }
-  } else if (FixedPcdGetBool (PcdIscpSupport)) {
-    for (Index = 0; Index < mAmdCoreCount; ++Index) {
-      CpuResetInfo.CoreNum = Index;
-      Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction (
-                   PeiServices, &CpuResetInfo );
-      ASSERT_EFI_ERROR (Status);
-
-      // Transition core to the RUN state
-      fCoreTransitionDone = FALSE;
-      do {
-        switch (CpuResetInfo.CoreStatus.Status) {
-        case CPU_CORE_POWERDOWN:
-          DEBUG ((EFI_D_ERROR, "Core[%d]: POWERDOWN -> POWERUP\n", Index));
-          CpuResetInfo.CoreStatus.Status = CPU_CORE_POWERUP;
-          break;
-         
-        case CPU_CORE_POWERUP:
-        case CPU_CORE_SLEEP:
-          DEBUG ((EFI_D_ERROR, "Core[%d]: POWERUP -> RESET\n", Index));
-          CpuResetInfo.CoreStatus.Status = CPU_CORE_RESET;
-          CpuResetInfo.CoreStatus.ResetVector = FixedPcdGet64 (PcdUefiEntryAddress);
-          break;
-
-        case CPU_CORE_RESET:
-          DEBUG ((EFI_D_ERROR, "Core[%d]: RESET -> RUN\n", Index));
-          CpuResetInfo.CoreStatus.Status = CPU_CORE_RUN;
-          break;
-
-        default:
-           if (CpuResetInfo.CoreStatus.Status == CPU_CORE_RUN) {
-             DEBUG ((EFI_D_ERROR, "Core[%d] at RUN state.\n", Index));
-           } else {
-             DEBUG ((EFI_D_ERROR, "Warning: Could not transition Core[%d] to RUN state.\n", Index));
-           }
-           fCoreTransitionDone = TRUE;
-          break;
-        }
-
-        // Transition core to next state
-        if (!fCoreTransitionDone) {
-          Status = PeiIscpPpi->ExecuteCpuResetTransaction (
-                       PeiServices, &CpuResetInfo );
-          ASSERT_EFI_ERROR (Status);
-        }
-      } while (!fCoreTransitionDone);
-    } // for
-  } // else
-
-  return Status;
-}
-
-
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.h b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.h
index 16ec3b837acd..a4893bcf4b50 100644
--- a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.h
+++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.h
@@ -20,14 +20,10 @@ 
 #include <Library/PcdLib.h>
 #include <Library/PeimEntryPoint.h>
 #include <Library/PeiServicesLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/HobLib.h>
 #include <Library/ArmLib.h>
 #include <Guid/ArmMpCoreInfo.h>
-#include <Ppi/EndOfPeiPhase.h>
-#include <Library/ArmSmcLib.h>
-#include <IndustryStandard/ArmStdSmc.h>
 
 #include <Ppi/IscpPpi.h>
 #include <Iscp.h>
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
index 06a633c4d82e..52dc47de7e97 100644
--- a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
@@ -33,7 +33,6 @@ 
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   AmdModulePkg/AmdModulePkg.dec
@@ -69,9 +68,7 @@ 
 
 [FixedPcd]
   gAmdStyxTokenSpaceGuid.PcdIscpSupport
-  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
   gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
-  gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress
   gAmdStyxTokenSpaceGuid.PcdCpuIdRegister
 
 [Depex]