From patchwork Tue May 3 11:10:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Punit Agrawal X-Patchwork-Id: 67062 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp529091qge; Tue, 3 May 2016 04:11:05 -0700 (PDT) X-Received: by 10.50.32.102 with SMTP id h6mr25555355igi.16.1462273865622; Tue, 03 May 2016 04:11:05 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id w186si407985iof.79.2016.05.03.04.11.05; Tue, 03 May 2016 04:11:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 115C46161C; Tue, 3 May 2016 11:11:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 9F4FD610B9; Tue, 3 May 2016 11:11:01 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 07C6A610B9; Tue, 3 May 2016 11:10:54 +0000 (UTC) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by lists.linaro.org (Postfix) with ESMTPS id B24F6610A9; Tue, 3 May 2016 11:10:52 +0000 (UTC) Received: from e105922-lin.cambridge.arm.com (e105922-lin.cambridge.arm.com [10.1.195.130]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with SMTP id u43BAmsD011165; Tue, 3 May 2016 12:10:48 +0100 Received: by e105922-lin.cambridge.arm.com (sSMTP sendmail emulation); Tue, 03 May 2016 12:10:48 +0100 From: Punit Agrawal To: leif.lindholm@linaro.org, ryan.harkin@linaro.org Date: Tue, 3 May 2016 12:10:43 +0100 Message-Id: <1462273843-20557-1-git-send-email-punit.agrawal@arm.com> X-Mailer: git-send-email 2.8.0.rc3 MIME-Version: 1.0 Cc: linaro-acpi@lists.linaro.org, linaro-uefi@lists.linaro.org, Punit Agrawal , steve.capper@arm.com Subject: [Linaro-uefi] [PATCH] Platforms/ARM: Juno: Update _PRT to provide interrupt type X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The PCI Routing Table (_PRT) for Juno does not specify the Interrupt trigger type and polarity. In the absence of this information, the kernel uses PCI default interrupt type (level triggered, active low) which is incompatible with GICv2 compliant interrupt controller such as on Juno. Absence of interrupt type leads to errors such as following in kernel boot log - [ 1.353696] genirq: Setting trigger mode 8 for irq 9 failed (gic_set_type+0x0/0x5c) [ 1.478286] genirq: Setting trigger mode 8 for irq 17 failed (gic_set_type+0x0/0x5c) [ 1.563723] genirq: Setting trigger mode 8 for irq 18 failed (gic_set_type+0x0/0x5c) Fix this issue by providing the correct information (level triggered, active high) to the kernel by using the PCI Link device. Signed-off-by: Punit Agrawal Reviewed-by: Graeme Gregory --- Hi, This patch to the OpenPlatformPkg for Juno ACPI tables fixes an issue I reported earlier[0]. All feedback welcome. Thanks, Punit [0] https://lists.linaro.org/pipermail/linaro-uefi/2016-April/001776.html Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 60 +++++++++++++++++------ 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl index 800d2cb..55b76d6 100644 --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl @@ -15,20 +15,43 @@ #include "ArmPlatform.h" /* - See Reference [1] 6.2.12 - "There are two ways that _PRT can be used. ... - In the second model, the PCI interrupts are hardwired to specific interrupt - inputs on the interrupt controller and are not configurable. In this case, - the Source field in _PRT does not reference a device, but instead contains - the value zero, and the Source Index field contains the global system - interrupt to which the PCI interrupt is hardwired." + See ACPI 6.1 Section 6.2.13 + + There are two ways that _PRT can be used. ... + + In the first model, a PCI Link device is used to provide additional + configuration information such as whether the interrupt is Level or + Edge triggered, it is active High or Low, Shared or Exclusive, etc. + + In the second model, the PCI interrupts are hardwired to specific + interrupt inputs on the interrupt controller and are not + configurable. In this case, the Source field in _PRT does not + reference a device, but instead contains the value zero, and the + Source Index field contains the global system interrupt to which the + PCI interrupt is hardwired. + + We use the first model with link indirection to set the correct + interrupt type as PCI defaults (Level Triggered, Active Low) are not + compatible with GICv2. */ -#define PRT_ENTRY(Address, Pin, Interrupt) \ - Package (4) { \ +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ Address, /* uses the same format as _ADR */ \ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \ - Zero, /* allocated from the global interrupt pool. */ \ - Interrupt /* global system interrupt number */ \ + Link, /* Interrupt allocated via Link device. */ \ + Zero /* global system interrupt number (no used) */ \ } /* @@ -36,7 +59,7 @@ "High word–Device #, Low word–Function #. (for example, device 3, function 2 is 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)." */ -#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt) +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge. @@ -45,6 +68,11 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM // // PCI Root Complex // + LNK_DEVICE(1, LNKA, 168) + LNK_DEVICE(2, LNKB, 169) + LNK_DEVICE(3, LNKC, 170) + LNK_DEVICE(4, LNKD, 171) + Device(PCI0) { Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge @@ -60,10 +88,10 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM // PCI Routing Table Name(_PRT, Package() { - ROOT_PRT_ENTRY(0, 168), // INTA - ROOT_PRT_ENTRY(1, 169), // INTB - ROOT_PRT_ENTRY(2, 170), // INTC - ROOT_PRT_ENTRY(3, 171), // INTD + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD }) // Root complex resources Method (_CRS, 0, Serialized) {