@@ -192,3 +192,79 @@ int cxl_dslbis_parse_entry(struct cdat_entry_header *header, void *arg)
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_dslbis_parse_entry, CXL);
+
+int cxl_sslbis_parse_entry(struct cdat_entry_header *header, void *arg)
+{
+ struct cdat_sslbis *sslbis = (struct cdat_sslbis *)header;
+ struct xarray *sslbis_xa = arg;
+ int remain, entries, i;
+
+ remain = sslbis->hdr.length - sizeof(*sslbis);
+ if (!remain || remain % sizeof(struct sslbis_sslbe)) {
+ pr_warn("Malformed SSLBIS table length: (%u)\n",
+ sslbis->hdr.length);
+ return -EINVAL;
+ }
+
+ /* Unrecognized data type, we can skip */
+ if (sslbis->data_type >= HMAT_SLLBIS_DATA_TYPE_MAX)
+ return 0;
+
+ entries = remain / sizeof(*sslbis);
+
+ for (i = 0; i < entries; i++) {
+ struct sslbis_sslbe *sslbe = &sslbis->sslbe[i];
+ u16 x = le16_to_cpu(sslbe->port_x_id);
+ u16 y = le16_to_cpu(sslbe->port_y_id);
+ struct node_hmem_attrs *hmem_attrs;
+ u16 dsp_id;
+ u64 val;
+ int rc;
+
+ switch (x) {
+ case SSLBIS_US_PORT:
+ dsp_id = y;
+ break;
+ case SSLBIS_ANY_PORT:
+ switch (y) {
+ case SSLBIS_US_PORT:
+ dsp_id = x;
+ break;
+ case SSLBIS_ANY_PORT:
+ dsp_id = SSLBIS_ANY_PORT;
+ break;
+ default:
+ dsp_id = y;
+ break;
+ }
+ break;
+ default:
+ dsp_id = x;
+ break;
+ }
+
+ hmem_attrs = xa_load(sslbis_xa, dsp_id);
+ if (xa_is_err(hmem_attrs))
+ return xa_err(hmem_attrs);
+ if (!hmem_attrs) {
+ hmem_attrs = kzalloc(sizeof(*hmem_attrs), GFP_KERNEL);
+ if (!hmem_attrs)
+ return -ENOMEM;
+ }
+
+ rc = check_mul_overflow(le64_to_cpu(sslbis->entry_base_unit),
+ le16_to_cpu(sslbe->value), &val);
+ if (unlikely(rc))
+ pr_warn("SSLBIS value overflowed!\n");
+
+ cxl_hmem_attrs_set(hmem_attrs, sslbis->data_type, val);
+ rc = xa_insert(sslbis_xa, dsp_id, hmem_attrs, GFP_KERNEL);
+ if (rc < 0 && rc != -EBUSY) {
+ kfree(hmem_attrs);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_sslbis_parse_entry, CXL);
@@ -518,6 +518,7 @@ static void cxl_ep_remove(struct cxl_port *port, struct cxl_ep *ep)
static void cxl_port_release(struct device *dev)
{
struct cxl_port *port = to_cxl_port(dev);
+ struct node_hmem_attrs *hmem_attrs;
unsigned long index;
struct cxl_ep *ep;
@@ -526,6 +527,9 @@ static void cxl_port_release(struct device *dev)
xa_destroy(&port->endpoints);
xa_destroy(&port->dports);
xa_destroy(&port->regions);
+ xa_for_each(&port->cdat.sslbis_xa, index, hmem_attrs)
+ kfree(hmem_attrs);
+ xa_destroy(&port->cdat.sslbis_xa);
ida_free(&cxl_port_ida, port->id);
kfree(port);
}
@@ -684,6 +688,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
xa_init(&port->dports);
xa_init(&port->endpoints);
xa_init(&port->regions);
+ xa_init(&port->cdat.sslbis_xa);
device_initialize(dev);
lockdep_set_class_and_subclass(&dev->mutex, &cxl_port_key, port->depth);
@@ -581,6 +581,7 @@ struct cxl_port {
struct cxl_cdat {
void *table;
size_t length;
+ struct xarray sslbis_xa;
} cdat;
bool cdat_available;
};
@@ -148,6 +148,25 @@ struct cdat_dslbis {
#define DSLBIS_MEM_MASK GENMASK(3, 0)
#define DSLBIS_MEM_MEMORY 0
+struct sslbis_sslbe {
+ __le16 port_x_id;
+ __le16 port_y_id;
+ __le16 value; /* latency or bandwidth */
+ __le16 reserved;
+} __packed;
+
+/* Sub-table 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */
+struct cdat_sslbis {
+ struct cdat_entry_header hdr;
+ u8 data_type;
+ u8 reserved[3];
+ __le64 entry_base_unit;
+ struct sslbis_sslbe sslbe[];
+} __packed;
+
+#define SSLBIS_US_PORT 0x0100
+#define SSLBIS_ANY_PORT 0xffff
+
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
@@ -169,4 +188,5 @@ int cxl_##x##_parse_entry(struct cdat_entry_header *header, void *arg)
cxl_parse_entry(dsmas);
cxl_parse_entry(dslbis);
+cxl_parse_entry(sslbis);
#endif /* __CXL_PCI_H__ */
@@ -83,7 +83,19 @@ static int cxl_switch_port_probe(struct cxl_port *port)
if (IS_ERR(cxlhdm))
return PTR_ERR(cxlhdm);
- return devm_cxl_enumerate_decoders(cxlhdm, NULL);
+ rc = devm_cxl_enumerate_decoders(cxlhdm, NULL);
+ if (rc < 0)
+ return rc;
+
+ if (port->cdat.table) {
+ rc = cdat_table_parse_sslbis(port->cdat.table,
+ cxl_sslbis_parse_entry,
+ (void *)&port->cdat.sslbis_xa);
+ if (rc <= 0)
+ dev_warn(&port->dev, "Failed to parse SSLBIS: %d\n", rc);
+ }
+
+ return 0;
}
static int cxl_endpoint_port_probe(struct cxl_port *port)
Provide a callback to parse the Switched Scoped Latency and Bandwidth Information Structure (DSLBIS) in the CDAT structures. The SSLBIS contains the bandwidth and latency information that's tied to the CLX switch that the data table has been read from. The extracted values are indexed by the downstream port id. It is possible the downstream port id is 0xffff which is a wildcard value for any port id. Coherent Device Attribute Table 1.03 2.1 Switched Scoped Latency and Bandwidth Information Structure (DSLBIS) Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v3: - Add spec section in commit header (Alison) - Move CDAT parse to cxl_switch_port_probe() - Use 'struct node_hmem_attrs' --- drivers/cxl/core/cdat.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/port.c | 5 +++ drivers/cxl/cxl.h | 1 + drivers/cxl/cxlpci.h | 20 ++++++++++++ drivers/cxl/port.c | 14 ++++++++- 5 files changed, 115 insertions(+), 1 deletion(-)