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[54.225.227.206]) by mx.google.com with ESMTP id f2si10873826igl.33.2016.05.06.07.29.44; Fri, 06 May 2016 07:29:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6991C6160E; Fri, 6 May 2016 14:29:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id BEC04615CD; Fri, 6 May 2016 14:29:40 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id CE69E61604; Fri, 6 May 2016 14:29:38 +0000 (UTC) Received: from mail-wm0-f48.google.com (mail-wm0-f48.google.com [74.125.82.48]) by lists.linaro.org (Postfix) with ESMTPS id EEBBB615CD for ; Fri, 6 May 2016 14:29:37 +0000 (UTC) Received: by mail-wm0-f48.google.com with SMTP id a17so81012377wme.0 for ; Fri, 06 May 2016 07:29:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7jUy4+O1XjXAVLQd9AN9DMcuGakDSnq8g+uxlzELUyU=; b=FXgaBqY5GiIa41tpKjzK4k6fbx3Imu5Vw4dMjS2ydZ+IBoa4Y2vDK2BNVDiMD85RSr PQhLrnmHKTymOjvcB/Xnox2MxGJRhXDdDHTFM6xgYOjTf+ImYrFy41MMgj3pwnSnodpw FHj3iNDhj7vynwMVjwNOlH13QgMpnxAQMWjEMiG2SVRaAt3VwScohqggB1cmVxzMqjuw P/pD4JqdpVyfpx68nrCmfTO1Jcmgl8Uwvs/vDkTd2gUZ6PXjVHE9Z/CXG5OA0GZxqaj3 YzIUXIWEC65tVc8FG0SgDvfv9gMWe2kwxVLkOIMqOQIKQslD9H5xO+2/Ihif0Ocusbpk 0O+A== X-Gm-Message-State: AOPr4FWv4ujO9UHcQKnVukmOvPEp7ob8jsQe52nQQmlmrjs4NgKtZJuvQnNScdUSFDtEkEJ0c/8= X-Received: by 10.195.6.65 with SMTP id cs1mr19325358wjd.8.1462544977023; Fri, 06 May 2016 07:29:37 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id y70sm8773836wmd.3.2016.05.06.07.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 May 2016 07:29:35 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@Lists.linaro.org, leif.lindholm@linaro.org Date: Fri, 6 May 2016 16:29:31 +0200 Message-Id: <1462544971-7875-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH] Platforms/AMD/Styx: disable legacy SMBIOS entry point generation X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The pre-v3.0 SMBIOS entry point only has a 32-bit field to store the address of the structure table, and so it does not make sense to attempt to generate such an entry point if you don't have any RAM below 4 GB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 2 ++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 581a2e02f9b8..892068f62025 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -507,6 +507,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 16b6f5469ca7..32d97c017b46 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -519,6 +519,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE !endif + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)