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[edk2,6/6] OvmfPkg/PlatformPei: provide 10 * 4KB of PCI IO Port space on Q35

Message ID 1462840655-1802-7-git-send-email-lersek@redhat.com
State New
Headers show

Commit Message

Laszlo Ersek May 10, 2016, 12:37 a.m. UTC 
This can accommodate 10 bridges (including root bridges, PCIe upstream and
downstream ports, etc -- see
<https://bugzilla.redhat.com/show_bug.cgi?id=1333238#c12> for more
details).

10 is not a whole lot, but closer to the architectural limit of 15 than
our current 4, so it can be considered a stop-gap solution until all
guests manage to migrate to virtio-1.0, and no longer need PCI IO BARs
behind PCIe downstream ports.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

---
 OvmfPkg/PlatformPei/Platform.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
1.8.3.1

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diff mbox

Patch

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 15a51f2abb03..fd60a9c91c1b 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -242,10 +242,20 @@  MemMapInitialization (
       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
         EfiReservedMemoryType);
     }
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+
+    //
+    // On Q35, the IO Port space is available for PCI resource allocations from
+    // 0x6000 up.
+    //
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+      PciIoBase = 0x6000;
+      PciIoSize = 0xA000;
+      ASSERT ((FixedPcdGet16 (PcdIch9AcpiPmBaseAddress) & 0xF000) < PciIoBase);
+    }
   }
 
   //
   // Add PCI IO Port space available for PCI resource allocations.
   //